Semiconductor image pickup device

Details Semiconductor image pickup device Semiconductor image pickup device

2000-12-08

2003-02-11

Kim, Robert H. (Department: 2882)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S2140RC

Reexamination Certificate

active

06518559

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor image pickup device provided with an image pickup pixel array. More specifically, this invention relates to a semiconductor image pickup device which sequentially selects pixels based on an X-Y address method and reads the output signal.
BACKGROUND OF THE INVENTION
FIG. 7
is a schematic block diagram of a conventional semiconductor image pickup device of X-Y address type. This semiconductor image pickup device comprises a pixel array
51
having a plurality of pixels arranged in a matrix, column direction read transistors (a column direction read transistor
58
n
and the like), column direction reset signal buffers (a column direction reset signal buffer
59
n
and the like), column direction read control line buffers (a column direction read control line buffer
60
n
and the like) provided for the respective columns of the pixel array
51
, and row direction reset signal buffers (a row direction reset signal buffer
61
m and the like) and row direction read control line buffers (a row direction read control line buffer
62
m
and the like) provided for the respective rows of the pixel arrays
51
.
Each pixel in the pixel array
51
, e.g., a pixel
52
mn
in row m and column n (the row m and the column n is an arbitrary matrix number of the pixel array
51
) comprises a light detecting element (photodiode)
53
mn
, a column direction reset transistor
54
mn
, a row direction reset transistor
55
mn
, an amplification AMI (Amplified MOS Imager) transistor
56
mn
and a row direction read transistor
57
mn
. The column direction reset transistor
54
mn
is connected to the charge accumulation section of the photodiode
53
mn.
The column direction reset signal buffer
59
n
receives a column direction reset signal XR
2
[n] and turns on or off the respective column direction reset transistors (the column direction reset transistor
54
mn
and the like) in column n depending upon the received signal. The column direction read signal buffer
60
n
receives a column direction read signal XS
2
[n] and turns on or off the column direction read transistor
58
n
depending upon the received signal. The row direction reset signal buffer
61
m receives a column direction reset signal YR
2
[m] and turns on or off the respective row direction reset transistors (the row direction reset transistor
55
mn
and the like) in row m depending upon the received signal. The row direction read signal buffer
62
m
receives a column direction read signal YS
2
[m] and turns on or off the respective row direction read transistors (the row direction read transistor
57
mn
and the like) in row m depending upon the received signal.
If both the column direction reset transistor
54
mn
and the row direction reset transistor
55
mn
are turned on, the voltage of the anode of the photodiode
53
mn
becomes a photodiode reset power voltage VDC, charges accumulated in the photodiode
53
mn
are discharged and the photodiode
53
mn
is turned into a reset state. That is, the pixel
52
mn
is reset. If both the column direction read transistor
58
n
and the row direction read transistor
57
mn
are turned on, a current according to the charges accumulated in the photodiode
53
mn
flows into the amplification AMI transistor
56
mn
and is outputted as an output signal. That is, read operation is carried out.
Further, the same power is supplied to the respective pixels (the pixel
52
mn
and the like), the column direction reset signal buffers (the column direction reset signal buffer
59
n
and the like), the column direction read signal buffers (the column direction read signal buffer
60
n
and the like), the row direction reset signal buffers (the row direction reset signal buffer
61
m
and the like) and the row direction read signal buffers (the row direction read signal buffer
62
m
and the like).
FIG. 8
is an explanatory view for the operation of the conventional semiconductor image pickup device. In the operation of the semiconductor image pickup device, two pixels on the pixel array
51
are simultaneously read and reset. For example, when a pixel
52
qs
in row q and column s is reset, a pixel
52
pr
in row p and column r is simultaneously read. The positions of the pixels to be reset and read move from a row q, column s position and a row p, column r position to a row q, column (s+1) position and a row p, column (r+1) position, respectively. When the reset and read of pixels in rows q and p are completed, reset and read target rows move to rows (q+1) and (p+1). After completing with the last row and column, the reset or read position returns to the leading row and column. In this way, scanning is carried out.
As for each pixel, a time after the pixel is reset until read or, in case of
FIG. 8
, a time for which the pixel position moves from the row p, column r position to the row q, column s position becomes a charge accumulation time for each photodiode. Namely, during this charge accumulation time, charges are accumulated in the charge accumulation section of the photodiode of each pixel. If both the corresponding row direction read transistor and the corresponding column direction read transistor are turned on, an output signal according to the accumulated charges is outputted.
FIG. 9
is a timing chart showing the operation of the conventional semiconductor image pickup device. In the operation of the conventional semiconductor image pickup device, first, the row direction reset signal YR
2
[m] is kept turned on (high level) until the resetting of the row m is completed. Then, when the column direction reset signal XR
2
[n] is turned on (A
2
in FIG.
9
), the pixel
52
mn
is reset. Thereafter, the row direction read signal YS
2
[m] is kept turned on until the read of the row m is completed. When the column direction reading signal XS
2
[n] is turned on (B
2
in FIG.
9
), the pixel
52
mn
is read.
During a charge accumulation time T
2
, since the pixel
52
mn
is reset until being read, the row direction reset signal YR
2
[m] is turned off after the reset selected row is moved to row (m+1), but the column direction reset signal XR
2
[n] is turned on and off a plurality of times (C
2
in FIG.
9
). This is because pixels in rows other than the row m and in column n are reset. The number of times the column direction reset signal XR
2
[n] is turned on and off corresponds to the positional relationship between a reset target row and a read target row. In case of
FIG. 8
, for example, the column direction reset signal XR
2
[n] is turned on and off (q−p−1) times.
In this way, if the column direction reset signal XR
2
[n] is turned on and off during the charge accumulation time T
2
, the column direction reset transistor
54
mn
is turned on and off and charging and discharging are carried out according to the parasitic capacitance between the gate and substrate of the column direction reset transistor
54
mn
. Part of charges thus charged and discharged flow into the photodiode
53
mn
, thereby generating a charge-pumping phenomenon so that the potential of the photodiode
53
mn
changes.
FIG. 10A
to
FIG. 10C
are explanatory views for the charge-pumping operation (charge-pumping phenomenon) of the conventional semiconductor image pickup device.
In the charge-pumping phenomenon of the semiconductor image pickup device, first, the row direction reset signal YR
2
[m] and the column direction reset signal XR
2
[n] are turned off (low level), a power supply voltage is applied to the gate control signal line
77
of the column direction reset transistor
54
mn
by the column direction reset signal buffer
59
n
, and the column direction reset transistor
54
mn
is turned off. During the charge accumulation time T
2
, the row direction reset signal YR
2
[m] is kept turned off and a current between the p+ source layer
71
an

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