Semiconductor IC device including ESD protection circuit

Details Semiconductor IC device including ESD protection circuit Semiconductor IC device including ESD protection circuit

1996-05-31

1998-07-21

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361118, 361127, H02H 900

Patent

active

057842353

ABSTRACT:
A surge protection circuit including a first MOSFET and a second MOSFET connected in series. The drain of the first MOSFET is connected to the input terminal and the source of the second MOSFET is grounded. The gate of the second MOSFET is grounded, whereas the gate of the first MOSFET is connected to a high potential power supply terminal. This makes it possible to equalize the voltages applied to the two MOSFETs constituting the surge protection circuit, and weakens the intensity of the internal electric field of respective MOSFETs, thereby prolonging the lifetime of the surge protection circuit. The surge protection circuit is particularly effective in a SOI LSI.

REFERENCES:
patent: 4989057 (1991-01-01), Lu
patent: 5321293 (1994-06-01), Mojaradi et al.
patent: 5473500 (1995-12-01), Payne et al.
McGraw-Hill, 2nd. Ed., 1988, pp. 648-650, "VLSI Technology", edited by S. M. Sze.
X. Guggenmos et al, "A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress", 1991 EOS/ESD Symposium Proceedings, pp. 74-82.
Mansun Chan et al, "ESD Reliability and Protection Schemes in SOI CMOS Output Buffers", IEEE Transactions on Electron Devices, vol. 42, No. 10, Oct. 1995, pp. 1816-1821.

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