Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-03-16
2002-01-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000, C365S189080
Reexamination Certificate
active
06335898
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semi-conductor IC (Integrated Circuit) device having a memory integrated therein, and more particularly to a technique having the effective application thereof to a semi-conductor IC device in which a memory having a plurality of data transmission lines such as data input/output lines (I/O lines) and a logic circuit are integrated on the same semiconductor chip.
In recent years, the progress of LSI's (Large Scale Integrated circuits) to high integration has been made so that it is being possible to integrate a large-capacity memory and a large-scale logic circuit or operation circuit on a semiconductor chip of about 1 cm square. In such chips, a very high speed equal to or higher than 1 G byte/sec can be attained as the rate of data transfer between the memory and the logic circuit or operation circuit by making the number of I/O lines of the memory equal to or greater than several hundreds. Therefore, such chips are expected to, for example, the use thereof for image processing or the like in which high-speed data transfer for a memory is required.
A first prior art applicable to such a purpose of use includes, for example, DRAM (Dynamic Random Access Memory) macros disclosed by Toshio Sunaga, et al., “DRAM Macros for ASIC Chips”, IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. 30, No. 9, September 1995, pp. 1006-1014. This reference has disclosed an LSI chip which includes the combination of a logic and a DRAM macro of 288K-bit (32K×9 bits) capacity having 9 (nine) I/O lines fabricated by 0.8 &mgr;m CMOS technique, and an LSI chip which includes the combination of a logic and a DRAM macro of 1.25M-bit (64K×18 bits) capacity having 18 (eighteen) I/O lines fabricated by 0.5 &mgr;m CMOS technique.
As a second relevant prior art, U.S. Pat. No. 5,371,896 (issued Dec. 6, 1994) has showed a system in which a parallel computing system having many processors and memories coupled to each other is integrated on the same semiconductor chip. In this second prior art, a plurality of memories and a plurality of processors are integrated on the same semiconductor chip, and the memories and the processors are coupled by a network including crossbar switches. The second prior art is characterized in that an SIMD (Single Instruction Multi Data Stream) operation and an MIMD (Multi Instruction Multi Data Stream) operation can be performed in a changing-over manner, as required. At the time of SIMD operation, one of the plurality of memories is used as an instruction memory and the remaining memories are used as data memories. An instruction from the instruction memory is given to the processors in common with each other. At the time of MIMD operation, a part of the memories used as the data memories at the time of SIMD operation are used as instruction memories so that instructions from the separate instruction memories are given to the individual processors. Data transfer paths between the individual memories and the processors can be changed over to each other in various ways by the crossbar network.
SUMMARY OF THE INVENTION
Though various other semiconductor IC devices having memories integrated therein are devised in addition to the above-mentioned ones, it is being possible to integrate a high-integration memory such as DRAM (Dynamic Random Access Memory) and a logic circuit on the same semiconductor chip, as in the above-mentioned first prior art and attention is given to this technique in the fields of image processing and so forth.
The present inventors have revealed that such a semiconductor IC device involves two subjects.
A first subject concerns a design system. The conventional high-integration memories as discrete memories, especially DRAM's are standardized in specification and hence they have a relatively long widely-used service life as products if they are manufactured once. Therefore, no great importance is attached to a design system for making a prompt design. However, a semi-condutor IC device having a high-integration memory such as DRAM and a logic circuit integrated on the same semiconductor chip as in the first prior art is needed, in many cases, for each specially fixed specification adapted to a specified application thereof. In general, therefore, a semiconductor maker will start in fabrication in compliance with a required specification after the acceptance of a requirement from a requester such as a user. Accordingly, the ability of prompt design is needed. In other words, the shortening of a time until the chip completion -from the start of chip design (or time to customers) is required. In addition, a variety of different memory capacities or kinds of operation circuits are required in accordance with the purpose of use. In order to satisfy such requirements for the period and the variety, it is necessary to make a reform from the design system.
A second subject concerns a coupling circuit for coupling a high-integration memory such as DRAM and a logic circuit which are integrated on the same semiconductor chip. In the case where the high-integration memory such as DRAM and the logic circuit are integrated on the same semiconductor chip, the mere integration thereof is difficult to bring about a large merit as compared with a discrete chip. If the cost and the required performance are taken into consideration, it is desirable that a large-capacity memory and a large-scale logic circuit such as operation circuit are integrated on a semiconductor chip of about 1 cm square so that several-hundred or more coupling lines can be ensured between the memory and the logic circuit to attain a high data transfer rate which is equal to or higher than, for example, 1 G byte/sec. Namely, it is desired that a coupling circuit for coupling the memory and the logic circuit is a high-speed and high-integration coupling circuit with which a data transfer path between the memory and the logic circuit (or operation circuit) can be changed in various ways.
The first prior art can overcome the first subject to some degree since it is possible to make the memory capacity variable by increasing and decreasing the number of DRAM macros, as required. In the first prior art, however, the number of I/O lines changes in proportion to the number of DRAM macros. Therefore, the first prior art has a problem that it is not possible to set the number of I/O lines and the memory capacity freely. Also, all peripheral circuits necessary for read/write operation are provided in each of DRAM macros having a relatively small capacity. Therefore, the first prior art has another problem that the overhead of the circuits becomes large if a multiplicity of DRAM macros are arranged. In order to make these problems more clear, the investigation will now be made in conjunction with the case where an LSI for image processing is constructed. For simplicity, it is assumed that each DRAM macro has a storage capacity of 256K bits and 8 (eight) I/O lines and the total number of I/O lines required in the LSI is 512. Then, the required number of DRAM macros is 64. The total storage capacity of the memory in this case amounts to 16M bits.
In the case where two-dimensional data is to be processed in the field of image processing, for example, in the case where a blurred image is to be reconstructed or in the case where characters or specified patterns are to be recognized, a high-speed ability is required even when such a memory capacity as mentioned in the above is not needed. In this case, if only the speed is taken into consideration, a multiplicity of DRAM macros of the first prior art can be arranged so that they are operated in parallel. However, there results in that the storage capacity of the memory becomes too large, thereby increasing the chip size. On the other hand, in the cage where three-dimensional data is to be processed, it is necessary to process a large amount of data at a high speed. It is possible to cope with this case by operating a multiplicity of DRAM macros in parallel, as mentioned above. However, there may be the
Ayukawa Kazushige
Fujita Ryo
Tanaka Hitoshi
Watanabe Takao
Yanagisawa Kazumasa
Elms Richard
Mattingly Stanger & Malur, P.C.
Nguyen Hie
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