Semiconductor heterostructures having reduced dislocation...

Details Semiconductor heterostructures having reduced dislocation... Semiconductor heterostructures having reduced dislocation...

2008-05-20

2008-05-20

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Having graded composition

C257S183000, C257SE21125

Reexamination Certificate

active

10646353

ABSTRACT:
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

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