Semiconductor heterostructure adapted for low temperature operat

Details Semiconductor heterostructure adapted for low temperature operat Semiconductor heterostructure adapted for low temperature operat

1987-12-23

1989-08-22

Wojciechowicz, Edward J.

357 4, 357 5, 357 15, 357 22, H01L 29161

Patent

active

048600679

ABSTRACT:
A low band gap semiconductor heterostructure having a surface adaptable to planar processing and all semiconductor properties supported by a fabrication constraint relaxing substrate that does not provide a low impedance parallel current path. A superconductor normal superconductor device of n-InAs-100 nanometers thick with niobium superconductor electrodes spaced 250 nanometers apart and a 100 nanometer gate in the space. The N-InAs is supported by an undoped GaAs layer on a semi-insulating GaAs substrate. A heterojunction field effect transistor device having a GaAlAs gate over a channel 100 nanometers thick on an undoped GaAs layer on a semi-insulating GaAs substrate.

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