Semiconductor heterojunction floating layer memory device and me

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

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257191, 257194, H01L 29205

Patent

active

054323568

ABSTRACT:
A semiconductor memory device comprises a non-doped thick barrier layer formed on the semiconductor substrate, an impurity doped floating conducting layer formed on the thick barrier layer, a thin barrier layer formed on the floating conducting layer and having an asymmetric barrier whose barrier height is higher on the side of the floating conducting layer, a channel layer formed on the thin barrier layer, and a first electrode and a second electrode formed on the channel layer. A write bias voltage which makes a potential of the second electrode higher than that of the first electrode is applied so as to inject electrons from the first electrode to the floating conducting layer through the thin barrier layer, thereby writing information in the floating conducting layer. A read bias voltage lower than the write bias voltage is applied between the first and the second electrodes, and the information stored in the floating conducting layer is read based on whether or not a current flows in the channel layer.

REFERENCES:
patent: 4905063 (1990-02-01), Beltram
patent: 5254863 (1993-10-01), Battersby

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