Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Patent
1992-08-21
1993-04-13
Prenty, Mark V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
H01L 2978
Patent
active
052025748
ABSTRACT:
A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anistropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.
REFERENCES:
patent: 2989385 (1961-06-01), Gianola et al.
patent: 3436623 (1966-12-01), Beer
patent: 3708360 (1970-06-01), Wakefield, Jr. et al.
patent: 3753774 (1973-08-01), Veloric
patent: 3753775 (1973-08-01), Robinson et al.
patent: 3764413 (1971-11-01), Kakizaki et al.
patent: 3886583 (1975-05-01), Wang
patent: 3906540 (1975-09-01), Hollins
patent: 3997367 (1976-12-01), Yau
patent: 4033026 (1977-07-01), Pashley
patent: 4045310 (1977-08-01), Jones et al.
patent: 4054989 (1977-10-01), Ho et al.
patent: 4074300 (1978-02-01), Sakai et al.
patent: 4075045 (1978-02-01), Rideout
patent: 4080719 (1978-03-01), Wilting
patent: 4085498 (1978-04-01), Rideout
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4109371 (1978-08-01), Shibata et al.
patent: 4113533 (1978-09-01), Okumura et al.
patent: 4114256 (1978-09-01), Thibault et al.
patent: 4128670 (1978-12-01), Gaensslen
patent: 4141022 (1979-02-01), Sigg et al.
patent: 4150389 (1979-04-01), Roessler
patent: 4152779 (1979-05-01), Tasch, Jr. et al.
patent: 4160683 (1979-07-01), Roche
patent: 4162176 (1979-07-01), Tsuda
patent: 4198250 (1980-04-01), Jecmen
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4209349 (1980-06-01), Ho et al.
patent: 4209350 (1980-06-01), Ho et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4259680 (1981-03-01), Lepselter et al.
patent: 4267011 (1981-05-01), Shibata et al.
patent: 4319395 (1982-03-01), Lund et al.
patent: 4330931 (1982-05-01), Liu
patent: 4343082 (1982-08-01), Lepselter et al.
patent: 4356040 (1982-10-01), Fu et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4369260 (1983-01-01), Younes
M. B. Vora, "Epitaxial Base Transistor", IBM Technical Disclosure Bulletin, pp. 1099-1100, vol. 13, No. 5, Oct. 1970.
Kircher, et al., "Fabricating a Gate Field-Effect Transistor", IBM Technical Disclosure Bulletin, pp. 646-648, vol. 13, No. 3, Aug. 1970.
M. B. Vora, "Schottky Barrier IGFET", IBM Technical Disclosure Bulletin, p. 1267, vol. 13, No. 5, Oct. 1970.
M. B. Vora, "FET-Bipolar Integration", IBM Technical Disclosure Bulletin, p. 1106, vol. 13, No. 5, Oct. 1970.
A. W. Chang, et al., "Transistor and Writing with Multi-step First Layer Metal", IBM Technical Disclosure Bulletin, pp. 578-579, vol. 21, No. 2, Jul. 1978.
V. L. Rideout, "Fabricating Low Resistance Interconnection Lines and FET Gates in a Single Step", IBM Technical Disclosure Bulletin, pp. 1250-1251, vol. 21, No. 3, Aug. 1978.
J. L. Dienes, et al., "Process for Realization of Submicron Geometries", IBM Technical Disclosure Bulletin, pp. 3628-3629, vol. 21, No. 9, Feb. 1979.
B. Meusemann, "Reactive Sputter Etching and Reactive Ion Milling-Selectivity, Dimensional Control, and Reduction of MOS-Interface Degradation", J. Vac. Sci. Technol., pp. 1886-1888, vol. 16, No. 6, Nov./Dec. 1979.
S. Nishimatsu, et al., "Grooved Gate MOSFET", Japanese Journal of Applied Physics, pp. 179-183, vol. 16, Supplement 16-1, 1977.
Chatterjee Pallab K.
Fu Horng-Sen
Tasch, Jr. Al F.
Donaldson Richard L.
Kesterson James C.
Prenty Mark V.
Stoltz Richard A.
Texas Instruments Incorporated
LandOfFree
Semiconductor having improved interlevel conductor insulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor having improved interlevel conductor insulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor having improved interlevel conductor insulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1157191