Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-06-05
2002-02-26
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S192000
Reexamination Certificate
active
06351000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, its production method and a semiconductor substrate structure of the device, and more particularly to: a semiconductor device constructed of an HEMT(High Electron Mobility Transistor), wherein a heterojunction is formed between adjacent compound semiconductor layers; a production method of the semiconductor device; and, a semiconductor substrate structure of the device.
2. Description of the Related Art
The HEMT, which is well known as a kind of FET(Field Effect Transistor), is not only capable of performing a high speed operation owing to the advantage of a so-called “high electron mobility” thereof, but also capable of operating in a superhigh frequency band, for example such as a microwave band and the like to output a large power with high efficiency. Consequently, the HEMT is widely used as a power transistor for use in a transmitter's output unit and the like mounted on a satellite communication instruments and the like.
FIG. 12
is a cross-sectional view of a first conventional semiconductor device constructed of the HEMT described above, illustrating a structure of the device. In this first conventional device, for example, as showning
FIG. 12
, an undoped InGaAs (indium gallium arsenide) layer
103
serving as a channel layer is formed on a semi-insulating undoped GaAs (gallium arsenide) substrate
101
through a buffer layer
102
, wherein the buffer layer
102
is formed of a GaAs layer or the like. Further formed on this undoped InGaAs layer
103
is an n-type AlGaAs layer
104
which serves as a carrier supply layer. Formed between the undoped InGaAs layer
103
and the n-type AlGaAs layer
104
is a heterojunction.
A gate electrode
105
which is made of, for example such as WSi (tungsten silicide) is formed in a central portion of the n-type AlGaAs (carrier supply) layer
104
to form a Schottky junction therein. Formed opposite sides of the gate electrode
105
are: a source contact layer
106
formed of, for example such as an n-type GaAs layer; and, a drain contact layer
107
formed of, for example such as an n-type GaAs layer. A source electrode
108
and a drain electrode
109
are formed in the source contact layer
106
and the drain contact layer
107
, respectively. An oxide film
110
is formed in a recess portion formed between the gate electrode
105
and each of the source contact layer
106
and the drain contact layer
107
, so that the gate electrode
105
is spaced apart from each of the source contact layer.
106
and the drain contact layer
107
by a distance corresponding to a film thickness of the oxide film
110
.
In the above structure shown in
FIG. 12
, carriers are supplied from the n-type AlGaAs layer
104
to a surface of the undoped InGaAs layer
103
to form a two-dimensional electron layer (hereinafter referred to as the two-dimensional electron gas layer)
112
. Electrons in this two-dimensional electron gas layer
112
produce a tunnel current. This tunnel current flows across the n-type AlGaAs layer
104
serving as a carrier supply layer, which makes it possible for the electrons to move between the source electrode
108
and the drain electrode
109
, and thereby producing a drain current for supporting in operation the FET. Here, an electron density of the two-dimensional electron gas layer
112
is determined by both of a film thickness and an impurity concentration (hereinafter referred to simply as the concentration) of the n-type AlGaAs layer
104
serving as a carrier supply layer.
By the way, in order to improve the performance of the FET, it is necessary to reduce in level a parasitic resistance appearing in a channel between: the gate electrode
105
; and, the source electrode
108
or the drain electrode
109
. In order to reduce such parasitic resistance, it is indispensable to increase the concentration of the n-type AlGaAs layer
104
which serves as a carrier supply layer located directly below the gate electrode
105
. On the other hand, when the concentration of the n-type AlGaAs layer
104
is increased, a so-called Schottky leak current (hereinafter referred to as the leak current) disadvantageously increases in a condition in which an effective gate breakdown strength disadvantageously decreases. Consequently, with respect to the concentration of the n-type AlGaAs layer
104
serving as a carrier supply layer, the trade-off in efforts to reduce the parasitic resistance is each of the increase of the leak current and the decrease of the gate breakdown strength.
Such trade-off problem mentioned above is solved by a second conventional semiconductor device disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 4-340234. In the second conventional semiconductor device, as shown in FIG.
13
: a first high concentration n-type AlGaAs layer
113
is formed on. the undoped InGaAs layer
103
to reduce the parasitic resistance, wherein the undoped InGaAs layer
103
serves as a channel layer; and, a second low concentration n-type AlGaAs layer
114
is formed directly under the gate electrode
105
to reduce the leak current and increase the gate breakdown strength, whereby the second low concentration n-type AlGaAs layer
114
is piled on the first high concentration n-type AlGaAs layer
113
to form a double layer portion of a structure shown in FIG.
13
.
Further, in this structure of
FIG. 13
, in order to effectively reduce the parasitic resistance, it is necessary to reduce the dimensions of each of the recess portions defined between the gate electrode
105
and each of the source contact layer
106
and the drain contact layer
107
. Consequently, in the second conventional semiconductor device shown in
FIG. 13
, the gate electrode
105
is formed self-alignedly with the recess's pattern of the source contact layer
106
.
However, since the degree of reduction of the parasitic resistance achieved in the above is not sufficient, it is necessary to further reduce the parasitic resistance. In order to further reduce the parasitic resistance, it is considered to be effective that the n-type AlGaAs layer
114
serving as a second carrier supply layer has its impurity concentration partially increased to partially increase the concentration of the second carrier supply layer in the recess portion.
However, as is clear from the structure shown in
FIG. 3
, all the n-type AlGaAs layer
114
serving as the second carrier supply layer including the above recess portion is so formed as to have the same concentration. As a result, it is not possible for the structure of
FIG. 3
to have only the recess portion thereof partially increased in impurity concentration. Consequently, when the second carrier layer is increased in impurity concentration to reduce the parasitic resistance in level, a portion directly under the gate electrode
105
is also increased in its impurity concentration together with the recess portion. This results in both the increase of the leak current and the reduction of the gate breakdown strength, as already described above.
A third conventional semiconductor device (shown in
FIG. 14
) is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 4-125939, in which an undoped AlGaAs layer corresponding to the n-type AlGaAs layer
114
serving as the second carrier supply layer shown in
FIG. 13
is selectively formed only in a position directly under the gate electrode
105
. In this third conventional semiconductor device, as shown in
FIG. 14
, an n-type AlGaAs layer
131
corresponding to a first carrier supply layer is formed on an undoped GaAs layer
123
serving as a channel layer. Further formed on this n-type AlGaAs layer
131
by a selective deposition process is an undoped AlGaAs layer
132
corresponding to the second carrier supply layer. Formed on this undoped AlGaAs layer
132
thus selectively deposited is the gate electrode
105
. The third conventional semiconductor device, which is shown in FIG.
14
and has the above const
Nadav Ori
Scully Scott Murphy & Presser
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