Semiconductor gate circuit having reduced dependency of input/ou

Details Semiconductor gate circuit having reduced dependency of input/ou Semiconductor gate circuit having reduced dependency of input/ou

1998-01-30

1999-10-26

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327264, 327544, H03K 301

Patent

active

059735333

ABSTRACT:
In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor. A gate circuit having a small dependency of an input/output characteristics on the power supply voltage is implemented without increasing the power consumption.

REFERENCES:
patent: 5376840 (1994-12-01), Nakayama
patent: 5541885 (1996-07-01), Takashima
patent: 5726946 (1998-03-01), Yamagata et al.

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