Semiconductor gate array device having an improved interconnecti

Details Semiconductor gate array device having an improved interconnecti Semiconductor gate array device having an improved interconnecti

1982-08-11

1986-01-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 307466, 307303, 307456, 357 45, 364491, H03K 19177, H03K 19003, H03K 19088, H01L 2700

Patent

active

045647739

ABSTRACT:
In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.

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Armstrong, "Applying CAD to Gate Arrays Speeds 32-Bit Minicomputer Design"; Electronics, pp. 167-173; 1/13/1981.
Dansky et al., "Custom Programmable Logic Arrays on STL Masterslices"; IBM Tech. Discl. Bull.; vol. 21, No. 4, pp. 1456-1460; 9/1978.
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IBM Journal of Research & Development, "Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array", Dansky, vol. 25, No. 2/3, May 1981, pp. 116-125.
Electro/80 Conference Record, "Using MECL 10K Macrocell Array as a Basic Building Block for Standard Product Development", King, vol. 5, May 13-15, 1980, pp. 1-7.
IEEE Spectrum, "Automating Chip Layout", Trimberger, vol. 19, No. 6, Jun. 1982, pp. 38-45.

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