Semiconductor gate array device compatible with ECL signals and/

Details Semiconductor gate array device compatible with ECL signals and/ Semiconductor gate array device compatible with ECL signals and/

1990-11-27

1992-07-21

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307455, 307456, H03K 190175, H03K 19086, H03K 1902

Patent

active

051325730

ABSTRACT:
A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a TTL output stage. When the device is to be used as a TTL input interface, the TTL input stage and the common output stage are coupled together and when the device is to be used as an ECL input interface, the ECL input stage and the common output stage are coupled together. When used as a TTL output interface, the common input stage and the TTL output stage are coupled together and when used as an ECL output interface, the common input stage and the ECL output stage are coupled together. Therefore, the input/output interfaces exhibit general applicability to meet the user's demands, yet enabling the layout areas of the input and output buffer portions to be decreased.

REFERENCES:
patent: 4527079 (1985-07-01), Thompson
patent: 4625129 (1986-11-01), Ueno
patent: 4636665 (1987-01-01), McLaughlin
patent: 4670673 (1987-06-01), Varadarajan
patent: 4697109 (1987-09-01), Honma et al.
patent: 4849659 (1989-07-01), West
patent: 4945265 (1990-07-01), Estrada
BiCMOS Technology for High Performance VLSI Circuits, Lee et al.; Aug. 1984.

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