Semiconductor gate array device

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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Details

257207, 257208, 257211, H01L 2710

Patent

active

061602752

ABSTRACT:
In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.

REFERENCES:
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 5083178 (1992-01-01), Otsu
patent: 5136356 (1992-08-01), Sakuda et al.
patent: 5281835 (1994-01-01), Tomita et al.
patent: 5343058 (1994-08-01), Shiffer II
patent: 5404034 (1995-04-01), Yin

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