Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-09-29
2003-01-21
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S050000, C257S529000, C438S131000, C438S467000, C438S600000
Reexamination Certificate
active
06509624
ABSTRACT:
TECHNICAL FIELD
The present invention relates most generally to integrated circuits. More particularly, the present invention relates to apparatuses and methods for providing fuses and antifuses in integrated circuit devices.
BACKGROUND OF THE INVENTION
In integrated circuit manufacturing, it is often desirable to select particular circuits from an array. For example, redundant parallel circuits may be formed and, after testing one circuit to verify that it functions properly, the other parallel circuit may be removed. Similarly, a parallel circuit which is normally isolated from other circuit elements may be added if needed. One method currently used to remove an unwanted circuit is to form programmable fuse elements in the circuit which are normally closed, then “blow” a fuse element with energy to open the circuit that is not selected. A method currently used to add a desired circuit is to form a programmable antifuse element in a circuit which is normally open then “blow” the antifuse element with energy to close the circuit which has been selected.
Various fuses and antifuses are provided in the conventional art in order to provide for redundant circuits or features to be selected or de-selected as appropriate. Many of the conventional fuses and antifuses formed within integrated circuit devices require the application of energy by means of external intervention into the integrated circuit. External power sources such as lasers are generally undesirable as they require the physical intervention of an external physical energy source which must be directed to a particular circuit feature, the alignment of which is very difficult to achieve, and they can also cause contamination when the fuse or antifuse element is blown. As such, fuses or antifuses which require power applied through external intervention, are generally not desirable. Thus, fuse or antifuse elements which are provided within the integrated circuit and which can be electrically programmed to blow, are more desirable.
In today's advancing integrated circuit manufacturing industry, the trend is towards the vertical integration of device features. Trench openings are formed within semiconductor substrates and various devices may be formed within the trench openings. These devices are vertically integrated downward into the substrate. An example of such a feature integrated into a trench opening is a trench capacitor which is commonly used in the integrated circuit manufacturing industry. Another feature provided in “vertical DRAM” technology, is a vertical transistor provided within a trench opening. A polysilicon or other semiconductive material is used as a plug formed within the trench opening and also serves as the transistor gate. In advanced integration schemes, a single trench opening may include both a trench capacitor formed in the lower portion of a particular trench opening, and a vertical trench transistor formed above and isolated from the trench capacitor, also in the same trench opening.
It would therefore be advantageous to incorporate the formation of fuses and antifuses into vertical DRAM processing technology. As such it is an object of the present invention to provide a method and structure which integrates fuse and antifuse structures into vertical DRAM processing technology.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides semiconductor fuses and antifuses formed within trench structures and which are formed using the process scheme also used to simultaneously form vertical trench transistors using vertical DRAM process technology.
The fuse element includes a polysilicon or other semiconductor material formed within an upper portion of a trench opening and which includes two conductive leads coupled to the top surface of the plug. In response to a predetermined voltage potential applied across the leads, the polysilicon or other semiconductor material “blows” and ceases to become conductive. In this manner a circuit may be opened.
In the antifuse, a thin dielectric layer such as silicon nitride serves as the antifuse element. In the antifuse, as in the fuse, a plug of polysilicon or another semiconductor material formed within the top portion of a trench opening is coupled to a first lead and is isolated from a second lead by means of the dielectric antifuse element. In response to a predetermined voltage potential applied across the leads, the antifuse dielectric element “blows” and allows for the conductive lead formed above it to be coupled to the plug formed of polysilicon or another semiconductor material formed below it. In this manner, the circuit becomes closed.
The present invention also provides a method for forming both the fuse and the antifuse structures. The method utilizes the sequence of process operations used to simultaneously form vertical trench transistors and the like, in other trench openings formed within the substrate. The polysilicon or other semiconductor material which is used as the gate electrode for vertical transistors formed in some trench openings, is also used to form the plug which forms either the fuse element, in the case of the fuse structure, or which contacts the dielectric antifuse element, in the case of the antifuse structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but not restrictive, of the invention.
REFERENCES:
patent: 6339559 (2002-01-01), Bertin et al.
patent: 6388305 (2002-05-01), Bertin et al.
patent: 6396121 (2002-05-01), Bertin et al.
Bergner Wolfgang
Divakaruni Rama
Nesbit Larry
Radens Carl J.
Kang Donghee
Loke Steven
Ratner & Prestia
Schnurmann H. Daniel
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