Semiconductor field effect device having channel stop and channe

Fishing – trapping – and vermin destroying

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437 45, H01L 21266

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active

051418827

ABSTRACT:
A method of forming a well on a semiconductor substrate and a transistor on the main surface of this well. A mask exposing a region for the well is formed on the main surface of the semiconductor substrate. Subsequently, ions of impurities for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using this mask with high energy giving concentration distribution of impurities which becomes maximum at a place deeper than a region for a transistor. Subsequently, ions of impurities of the same conductivity type as that of ions for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using the mask with low energy giving concentration distribution of impurities in which impurities stay in the region for the channel of the transistor. According to this method, since the formation of the well and channel ion implantation are performed using the same mask, the number of photolithography processes is decreased. In addition, in forming the well, since it is not necessary to diffuse the impurity ions by heat, manufacturing time can be shortened. In addition, since ions of impurities are implanted in the channel region of the transistor, a punch through of the transistor can be prevented.

REFERENCES:
patent: 4710477 (1987-12-01), Chen
patent: 4717683 (1988-01-01), Parrillo et al.
patent: 4784968 (1988-11-01), Komori et al.
patent: 4968639 (1990-11-01), Bergonzoni
Wolf, "Silicon Processing for the VLSI Era", vol. 1, Lattice Press, 1986, pp. 280-295 and 325-327.
A. Lewis et al., "Latchup Performance of Retrograde & Conventional n-Well CMOS Technologies", IEEE Transactions on Electron Devices, vol. ED-34, No. 10 (Oct. 1987), pp. 2156-2163.
A. Stolmeijer, "A Twin-Well CMOS Process Employing High-Energy Ion Implantation", IEEE Transactions on Electron Devices, vol. ED-33, No. 4 (Apr. 1986), pp. 450-457.
"VLSI Technology" excerpt edited by S. M. Sze, McGra-Hill International Book Co.

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