Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2000-12-08
2002-06-11
Johnson, Timothy M. (Department: 2623)
Image analysis
Applications
Manufacturing or product inspection
C382S194000, C382S203000
Reexamination Certificate
active
06404911
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor failure analysis system and a semiconductor checking apparatus and particularly, relates to a semiconductor failure analyzing system adapted for analysis the cause of a failure in a semiconductor wafer production and a semiconductor checking apparatus used in the failure analysis system.
According to one to conventional semiconductor failure analysis system, namely, JP-A-61-243378 a failure analysis system is provided in which: distribution patterns of points obtained by an electrical test and an indication of whether the quality of a subject under inspection is good or bad are classified into basic patterns so that the basic patterns are stored in a storage device; information indicating a plurality of possibilities that a failure has occurred in the subject under inspection is generated correspondingly to basic patterns obtained from basic failure information which can be considered with respect to the all basic patterns stored in the storage device; and the coordinates of points at which the occurrence of the failure is estimated are automatically transferred to an observation apparatus.
In the conventional system, there is however no consideration that means for observing information concerned with results of failure analysis systematically from a large number of viewpoints is provided in an user interface of the system. That is, there is no consideration that information concerned with results of failure analysis, such as display indicating fail bits on the whole of a wafer, display indicating the distribution of fail bits on an arbitrary chip, enlarged display indicating the distribution of fail bits in a partial area of a chip, and so on, is used speedily and smoothly. Whether the aforementioned information is to be displayed or not to be displayed, it is necessary to operate a display unit to switch the scene on the display unit to a new scene. Accordingly, operations which can be very troublesome for users are often required.
Further, in the conventional system, there has been proposed no method in which the sizes of memory cells can be confirmed visually with respect to the user interface of the system when information is displayed.
Further, in the conventional semiconductor failure analysis system, no consideration is given that errors may occur when the coordinates of points at which the occurrence of the failure is estimated are transferred to the observation apparatus because different coordinate reference points are used. Further, patterns of generation of fail bits are classified, but there is no specific rule for the classification. In the conventional system, therefore, all causes of failure distributions are estimated so that a small number of basic patterns thus classified have one-to-one correspondence with the causes of the failure. In the conventional system, however no consideration is given that a plurality of causes of the failure correspond to one and the same pattern of fail bits, though such correspondence must be thought of. Further, because the causes related to the basic patterns are difficult to determine, a large time is required for examining the true cause of the failure. Further, because there is no consideration that the relation between the pattern of generation of fail bits and the cause of the failure varies in accordance with the subject under inspection, the conventional system cannot be adapted to multikind subjects of inspection.
Further, because there has not been proposed a function of managing the situation of occurrence of fail bits statistically on the basis of the classified basic patterns to thereby feed results of the management back to a production process, the conventional system has a risk that the occurrence of a failure may be detected later when the failure has occurred in the production process.
In addition, though a micro analyzing method in which the situation of occurrence of fail bits in a wafer or in a chip is analyzed bit by bit is employed in the conventional system, there has not been proposed a macro analyzing method in which the patterns of generation of fail bits are categorized so that macro analysis is performed by using the category thereof.
SUMMARY OF THE INVENTION
The present invention is designed to solve the aforementioned problems in the prior art.
A first object of the present invention is to provide a semiconductor failure analysis system in which the cause of a failure is examined easily, accurately and speedily with the advance of integration of semiconductor memory when fail bits are subjected to failure analysis.
A second object of the present invention is to provide a semiconductor failure analysis system in which unification of coordinate systems varying in accordance with respective inspection apparatuses and correction of measurement errors dependent on the respective apparatuses can be performed so that failure analysis can be carried out accurately and speedily by using a plurality of inspection data with the advance of integration of the semiconductor memory.
A third object of the present invention is to provide a semiconductor checking apparatus in which measurement errors can be corrected for the failure analysis of a semiconductor.
The above first object of the present invention is achieved by a semiconductor failure analysis system which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for inspecting the failure information concerned with the failure of the semiconductor, a storage unit for storing information concerned with the design of the semiconductor, an analysis unit for analyzing the failure information on the basis of output information outputted from the failure information collection unit, output information outputted from the inspection unit and design information stored in the storage unit, a display unit for displaying at least one of the result of analysis of the analysis unit and the failure information, a failure cause estimation unit for estimating the cause of the failure information, and a feeding unit for feeding the estimated cause of the failure back to a process in which the failure has occurred.
The above second object of the present invention is achieved by a semiconductor failure analysis system which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for inspecting the failure information of the semiconductor by using a plurality of inspection apparatuses, an analysis unit for analyzing the failure information on the basis of output information outputted from the failure information collection unit and output information outputted from the inspection unit, a display unit for displaying at least one of the result of analysis of the analysis unit and the failure information, and a correction unit for correcting measurement errors between the plurality of inspection apparatuses.
The above third object of the present invention is achieved by a semiconductor checking apparatus which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for inspecting the failure information of the semiconductor, a display unit for displaying at least one of output information outputted from the inspection unit and the failure information, and a correction unit for correcting measurement errors in the inspection unit.
In the present invention, failure information is analyzed on the basis of information outputted from the failure information collection unit, information outputted from the inspection unit and design information stored in the storage means. Accordingly, the failure information can be analyzed by referring to information concerned with the arrangement of memory cells correspondingly to the kind of each chip, so that a coordinate system can be set on the basis of one chip. Further, in
Ishihara Kazuko
Ishikawa Seiji
Miyamoto Yoshiyuki
Miyazaki Isao
Nakazato Jun
Hitachi , Ltd.
Johnson Timothy M.
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