Semiconductor fabrication method of forming a master layer to co

Details Semiconductor fabrication method of forming a master layer to co Semiconductor fabrication method of forming a master layer to co

1997-03-14

1998-11-17

Chaudhari, Chandra

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Interconnecting plural devices on semiconductor substrate

438129, 438599, H01L 2182

Patent

active

058375570

ABSTRACT:
Each circuit block of a plurality of circuit blocks on a semiconductor substrate is imaged in an exposure field defined by a reticle. The circuit blocks are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The circuit blocks are globally interconnected by depositing a blanket metal layer, masking the metal layer and etching the metal layer using a stitching reticle having an exposure field overlapping the plurality of circuit blocks. The combination of reticle-imaged circuit blocks allows each individual circuit block to be fabricated independently, using independent imaging resolution, layout rules, design rules, different polysilicon sizes and source/drain region sizes and the like. In addition different reticles, including different reticle types, resolutions and qualities may be used to construct the various circuit blocks. Different imaging technologies may be used to construct the independent circuit blocks, including X-ray, I-line, H-line, ion-beam and electron-beam irradiation, for example. While the different circuit blocks are independently constructed, the circuit blocks are globally interconnected using the blanket metal layer so that overall circuit size is reduced, circuit quality is enhanced, fabrication time and costs are reduced, and performance is increased. A plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are globally interconnected using a blanket metal layer that is imaged using a stitch mask and etch operation that combines and electrically connects the individual integrated chips.

REFERENCES:
patent: 4969029 (1990-11-01), Ando et al.
patent: 5252507 (1993-10-01), Hively et al.
patent: 5252508 (1993-10-01), Masuda
patent: 5444000 (1995-08-01), Ohkubo et al.

Affiliated with

Also associated with

Rating

Semiconductor fabrication method of forming a master layer to co does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor fabrication method of forming a master layer to co, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor fabrication method of forming a master layer to co will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-883776