Semiconductor fabrication employing barrier atoms incorporated a

Details Semiconductor fabrication employing barrier atoms incorporated a Semiconductor fabrication employing barrier atoms incorporated a

1997-09-04

1998-12-29

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 257510, H01L 21302

Patent

active

058541217

ABSTRACT:
A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.

REFERENCES:
patent: 5506168 (1996-04-01), Morita et al.
patent: 5545290 (1996-08-01), Douglas

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