Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-03-12
1999-11-09
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438759, 438760, 438763, 438782, H01L 21463
Patent
active
059813547
ABSTRACT:
An improved planarization process for a trench dielectric is presented. A shallow trench isolation structure is formed into the semiconductor substrate. A thin oxide layer is grown upon the trench floor and upon the trench sidewalls, and then a trench dielectric, preferably TEOS deposited using a chemical-vapor deposition CVD process, is deposited into the trench dielectric and upon the semiconductor substrate. The upper surface of the trench dielectric conforms to the underlying contour defined by the shallow trench and the semiconductor substrate. Subsequent device formation requires a substantially planar semiconductor. Conventionally, a combination of masking and etching are used, prior to chemical-mechanical polishing ("CMP"), to aid the planarization process. The extra steps add cost and unnecessary complexity to the process. An alternative planarization process is proposed which uses hydrogen silsequioxane-based flowable oxide ("HSQ"). The HSQ is spin-on deposited upon the conformal trench dielectric in liquid form. After deposition the HSQ is heated which causes it to reflow and produce a substantially planar upper surface. The reflow parameters (such as temperature and time) are chosen so that the HSQ has a polish rate which is approximately equal to the polish rate of the trench dielectric. A chemical-mechanical polish ("CMP") is then used to entirely remove the HSQ layer and a portion of the trench dielectric exterior to the shallow trenches. Since the HSQ is polished at the same rate as the trench dielectric, the upper surface of the trench dielectric after the polish is substantially planar and approximately at the same level as the upper surface of the semiconductor substrate.
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Hause Fred N.
Kadosh Daniel
Spikes Thomas E.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Eaton Kurt
Monin, Jr. Donald L.
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