Electrolysis: processes – compositions used therein – and methods – Electrolytic erosion of a workpiece for shape or surface... – With irradiation or illumination
Reexamination Certificate
2000-11-22
2003-02-18
Nguyen, Nam (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic erosion of a workpiece for shape or surface...
With irradiation or illumination
C205S656000
Reexamination Certificate
active
06521118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for etching semiconductor materials.
2. Description of the Related Art
Many devices fabricated from silicon and other semiconductors must be truly three-dimensional. Some examples of these three-dimensional devices include micromechanical sensors and actuators, electrostatically driven micro-motors, and valve systems. Other three-dimensional structures are optical gratings and lenses, isolation trenches, mesas and via holes.
Three-dimensional structures formed from silicon and other semiconductor substrates are generally produced by anisotropic etching processes. At present, silicon is usually removed by simple chemical etching, that is, by immersing silicon specimens in a liquid bath of the chemical etchants. These are usually hydrofluoric solutions, strong alkalis such as KOH, or ethylene diamine-pirocathecol (EDP).
There are several limitations inherent in the etching techniques presently known and used in the art. The principal problem is a lack of control over the rate of silicon dissolution during the etching process. This lack of control restricts the utility of the micromachining methods presently known and used in the art.
Furthermore, at present, there is only one electrochemical technique which is reasonably effective in increasing the rate of silicon etching. This technique combines anodic biasing in aggressive HF solutions with illumination. However, the use of etchants like hydrofluoric acid, which are highly corrosive and environmentally hazardous, gives rise to serious problems in production and waste disposal.
In contrast to etching in HF, etching of silicon in aqueous alkaline solutions, e.g. NaOH or KOH solutions, is performed without electrical biasing. This is because the anodic biasing of silicon in alkaline solutions results in inactivation of the silicon, so that etching stops. Even in such aggressive media as KOH, silicon remains active only in a very narrow potential range more positive than corrosion potential E
corr.
Biasing of silicon in this range does not significantly affect the etching rate in comparison to silicon dissolution without biasing. Thus, except when etching in HF, anodic bias is not used for etching silicon.
Little data is available concerning the electrochemical behavior of semiconductors under cathodic bias. Gerisher & Mindt, Electrochim. Acta, 13, 1329, (1968) pointed out the feasibility of the cathodic decomposition of semiconductors. Additionally, they showed the reduction of such semiconductors as ZnO, CdO, CuS, etc. to their metal states.
It has also been shown by Glembocki et al., J. Electrochem. Soc., Vol. 132, 145-151 (1985), and by Seidel, in “Integrated Micro-Motion Systems—Micromachining, Control and Applications,” F. Harashima, Ed.; Elsevier Science Publishers, B.V., 1990 pp.51-68, that applying cathodic bias to silicon causes a decrease in the dissolution rate of n-type silicon and has almost no affect on the dissolution of p-type specimens. These experiments were carried out in KOH solutions in the potential range from −6 to +0.5 V relative to the open circuit potential (OCP).
Accordingly, there is a need for an improved method for micromachining three-dimensional structures that is electrochemically controlled, more versatile, and safer to the environment.
SUMMARY OF THE INVENTION
The present invention seeks to provide an improved method for etching three-dimensional structures in semiconductor materials, which method enables greater control of the rate of the etching process, is applicable to a wider variety of semiconductor materials, and is environmentally safer than etching methods currently known and in use in the art.
There is thus provided, in accordance with a preferred embodiment of the invention, a process for etching a semiconductor material, comprising the steps of
(a) providing an electrochemical cell containing an etching electrolyte, the etching electrolyte being selected from the group of acidic electrolyte solutions, alkaline solutions, neutral solutions, and molten electrolytes;
(b) immersing the semiconductor material in the etching electrolyte, whereby at least one surface of the semiconductor material contacts the etching electrolyte;
(c) after step (b), negatively biasing the semiconductor material; and
(d) while negatively biasing the semiconductor material, illuminating at least part of the at least one surface of the semiconductor material which contacts the etching electrolyte with light selected from the group of ultraviolet, visible, and infrared light.
In one preferred embodiment of the invention, the etching electrolyte is selected from among acidic aqueous solutions, alkaline aqueous solutions, and neutral aqueous solutions. In another preferred embodiment of the invention, the etching electrolyte is a molten salt.
In another preferred embodiment of the invention, the semiconductor material is masked and patterned prior to immersion. In accordance with this preferred embodiment of the invention, the process of the invention comprises the steps of:
(i) providing an electrochemical cell containing an etching electrolyte, the etching electrolyte being selected from the group of acidic electrolyte solutions, alkaline solutions, neutral solutions, and molten electrolytes;
(ii) masking and patterning the semiconductor material with a masking material which is electrically insulating and less susceptible to the etching electrolyte than is the semiconductor material, whereby to provide a masked semiconductor material having at least one masked and at least one exposed surface;
(iii) immersing the masked semiconductor material in the etching electrolyte, whereby at least one exposed surface of the masked semiconductor material contacts the etching electrolyte;
(iv) after step (iii), negatively biasing the masked semiconductor material until the potential reaches a negative voltage value; and
(v) while negatively biasing the masked semiconductor material, illuminating at least part of the at least one exposed surface of the masked semiconductor material which contacts the etching electrolyte with light selected from the group of ultraviolet, visible, and infrared light.
In one preferred embodiment of the invention, step (ii) of the process comprises masking and patterning the semiconductor material with a masking material which is inert to the etching electrolyte.
In another preferred embodiment of the invention, step (b), or correspondingly, step (iii) of the process comprises immersing the semiconductor material in the etching electrolyte, until the open circuit potential of the semiconductor material reaches a steady state value. This preferred embodiment is especially preferred when the etching electrolyte is a strong alkaline solution, such as KOH. In yet another preferred embodiment of the invention, the semiconductor material is immersed in the etching electrolyte until the open circuit potential of the semiconductor material reaches a value of minus 1.1 V or a value more negative than minus 1.1 V, preferably from about minus 1.1 V to about minus 1.5 V, with respect to a Standard Calomel Electrode (SCE). This preferred embodiment is also especially preferred when the etching electrolyte is a strong alkaline solution, such as KOH.
In another preferred embodiment of the invention, step (c), or correspondingly, step (iv) of the process comprises negatively biasing the semiconductor material until the potential reaches a value of about minus 5 volts (SCE) or a value more negative than minus 5 volts (SCE).
In still another preferred embodiment of the invention, step (d), or correspondingly, step (v) of the process comprises illuminating the semiconductor material with light selected from the group of ultraviolet, visible, and infrared fight while negatively biasing said semiconductor material to a potential of about minus 5 volts (SCE) or a value more negative than minus 5 volts (SCE).
Thus, in an especially preferred embodiment of the invention, the process comprises:
(a)
Kovler Mark
Nemirovsky Yael
Starosvetsky David
Yahalom Joseph
Ladas & Parry
Nguyen Nam
Parsons Thomas H.
Technion Research and Development Foundation
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