Semiconductor ESD protection circuit

Details Semiconductor ESD protection circuit Semiconductor ESD protection circuit

1999-05-20

2001-06-19

Sherry, Michael J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C361S091500

Reexamination Certificate

active

06249413

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of semiconductor devices, and more particularly, to an improved semiconductor ESD protection circuit.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) phenomena. An IC may be exposed to ESD from many sources. The major source of ESD exposure to ICs is from the human body, and is known as the Human Body Model (HBM) ESD source. A charge of about 0.6 &mgr;C can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Any contact by a charged human body with a grounded object, such as the pin of an IC, can result in a discharge for about 100 nS with peak currents of several amperes to the IC.
A second source of ESD is from metallic objects, and is known as the machine model (MM) ESD source. The MM ESD source is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD model can result in ESD transients with significantly higher rise times than the HBM ESD source.
A third ESD model is the charged device model (CDM). Unlike the HBM ESD source and the MM ESD source, the CDM ESD source includes situations where the IC itself becomes charged and discharges to ground. Thus, the ESD discharge current flows in the opposite direction in the IC than that of the HBM ESD source and the MM ESD source. CDM pulses also have very fast rise times compared to the HBM ESD source.
The most common protection schemes used in metal-oxide semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with a nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism found in then MOS protection device operating as a parasitic bipolar transistor in snapback conditions is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Such substrate biasing can be effective at improving the response of a multi-finger metal oxide semiconductor (MOS) transistor that is used to conduct an ESD discharge to ground. Nevertheless, substrate biasing can cause the threshold voltages for devices to change from their nominal values, which may affect device operation. In addition, substrate biasing under steady-state conditions causes heat generation and increases power losses. Thus, although substrate biasing has the benefit of increasing the response of ESD protection of multi-finger MOS transistors, the additional problems caused by substrate biasing may limit its effectiveness.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for improved ESD protection circuitry. In particular, a need has arisen for a circuit for biasing the substrate of ESD protection circuitry that does not result in the problems of heating, power losses, and device malfunction associated with existing substrate biasing circuits.
One aspect of the present invention provides protection circuitry that protects an integrated circuit from an ESD pulse. The protection circuitry includes discharge circuitry on a substrate that discharges an ESD pulse to the integrated circuit to ground. The protection circuitry also includes a substrate bias generator that uses a portion of the ESD pulse's energy to bias the substrate of the discharge circuitry.
Another aspect of the present invention provides a method for protecting an integrated circuit from an ESD pulse. The method includes receiving the ESD pulse at discharge circuitry on a substrate at the input of the integrated circuit. The method further includes diverting a portion of the ESD pulse to a substrate bias generator and biasing the substrate of the protection circuitry with the portion of the ESD pulse for the duration of the ESD pulse.
Yet another aspect of the present invention provides protection circuitry that protects an integrated circuit from an ESD pulse. The protection circuitry includes discharge circuitry on a substrate having an input, a gate, and a ground node and the discharge circuitry conducts the ESD pulse from the input to ground. The protection circuitry also includes a substrate bias generator that uses a portion of the ESD pulse's energy to bias the substrate of the discharge circuitry. The substrate bias generator includes a resistor that generates a voltage from the portion of the ESD pulse's energy and a guard ring coupled to the resistor that provides the voltage to the discharge circuitry's substrate.
The present invention provides several technical advantages. One important technical advantage of the present invention is that it provides protection to the devices on an IC from various ESD sources. The ESD protection circuitry of the present invention is effective to protect circuitry on the IC from the HBM, MM, and CDM ESD sources.
Another technical advantage of the present invention is that it provides substrate biasing of the ESD protection circuitry only during an ESD event. Therefore, the drawbacks associated with prior substrate biasing schemes are not experienced with the present invention.
Another important technical advantage of the present invention is that energy for biasing the substrate of the ESD protection circuitry is provided by the ESD pulse. This scheme eliminates the need to supply an additional voltage source to the ESD protection circuitry.
Yet another technical advantage of the present inventive ESD protection scheme is that it may be implemented using standard semiconductor processing techniques. The present ESD protection circuitry, therefore, does not add significant processing time or expense to the IC.


REFERENCES:
patent: 4855620 (1989-08-01), Durvvury et al.
patent: 5290724 (1994-03-01), Leach
patent: 5528188 (1996-06-01), Au et al.
patent: 5940258 (1999-08-01), Duvvury

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