Semiconductor embedded layer technology including permeable base

Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With base region having specified doping concentration...

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257523, 257552, 257587, 257617, H01L 27082, H01L 2900, H01L 27102, H01L 2930

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052987876

ABSTRACT:
A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).

REFERENCES:
patent: 2524033 (1950-10-01), Bardeen
patent: 2569347 (1951-09-01), Shockley
patent: 2820154 (1958-01-01), Kurshan
patent: 3121809 (1964-02-01), Atalla
patent: 3250966 (1966-05-01), Rose
patent: 3250967 (1966-05-01), Rose
patent: 3274461 (1966-09-01), Teszner
patent: 3322581 (1967-05-01), Hendrickson et al.
patent: 3370184 (1968-02-01), Zuleeg
patent: 3372069 (1968-03-01), Bailey et al.
patent: 3375418 (1968-03-01), Garnache et al.
patent: 3381189 (1968-04-01), Hinkle, Jr. et al.
patent: 3386864 (1968-06-01), Silvestri et al.
patent: 3394289 (1968-07-01), Lindmayer
patent: 3401449 (1968-09-01), Shaw
patent: 3425879 (1969-02-01), Shaw et al.
patent: 3497777 (1970-02-01), Teszner
patent: 3564358 (1971-02-01), Hahnlein
patent: 3571675 (1971-03-01), Faust
patent: 3582410 (1971-06-01), Chapelle
patent: 3597270 (1971-08-01), Scott-Monck et al.
patent: 3614560 (1971-10-01), Anantha
patent: 3676732 (1972-07-01), Gabor
patent: 3748548 (1973-07-01), Haisty et al.
patent: 3751723 (1973-08-01), Shirn et al.
patent: 3824133 (1974-07-01), D'Asaro et al.
patent: 3860946 (1975-01-01), Shumka
patent: 3929527 (1975-12-01), Chang et al.
patent: 3938241 (1976-02-01), George et al.
patent: 3999281 (1976-12-01), Goronkin et al.
patent: 4059461 (1977-11-01), Fan et al.
patent: 4126899 (1978-11-01), Lohstroh et al.
patent: 4127861 (1978-11-01), Deneuville
patent: 4190850 (1980-02-01), Tihanyi et al.
patent: 4468683 (1984-08-01), Dahlberg
patent: 4495511 (1985-01-01), Yoder
patent: 4510016 (1985-04-01), Chi et al.
patent: 4677451 (1987-06-01), Parsons et al.
patent: 4901121 (1990-02-01), Gibson et al.
patent: 4903090 (1990-02-01), Yokoyama
IBM Technical Disclosure Bulletin, "Monolithic circuit interconnections", Seto et al., pp. 922-p. 923, vol. 9, No. 7, Dec. 1966.
Electronics, Mar. 13, 1964, "Metal Base Transistor-Pushes Back Frequency Barrier", pp. 42-46, by Geppert et al.
Journel Brit. I.R.E., May 1960, "A Proposed Space-Charge-Limited Dielectric Triode" by Wright, pp. 337-349.
Anantha, N. G., "Fabricating a Metal Base Transistor", IBM Technical Disclosure Bulletin, vol. 13, No. 8, Jan. 1970, pp. 2149-2150.
Nishizawa, J., T. Terasaki and J. Shibata, "Field-Effect Transistor Versus Analog Transistor (Static Induction Transistor)", IEEE Transactions on Electron Devices, vol. ED-22, No. 4, Apr. 1975, pp. 185-197.
Nishizawa, J., "Device Applications: The Static Induction Transistor and Integrated Circuits", Crystal Growth Theory Techniques, 1978, pp. 98-107.
Mochida, Y., J. Nishizawa) T. Ohmi and R. Gupta, "Characteristics of Static Induction Transistors: Effects of Series Resistance", IEEE Transactions on Electron Devices, vol. ED-25, No. 7, Jul. 1978, pp. 761-767.
Zuleeg, R., "Multi-Channel Field-Effect Transistor Theory and Experiment", Solid State Electronics, vol. 10, pp. 559-576.
Ozawa, O., "Temperature Dependence of Triodelike JFET Drain Current After Pinchoff", IEEE Transactions on Electron Devices, Jun. 197, pp. 768-769.
Teszner, S. and R. Gicquel, "Gridistor--A New Field-Effect Device", Proceedings of the IEEE, Dec. 1964, pp. 1502-1513.
Esaki, L. and L. L. Chang, "Ultimate FET Structures", Proceedings of the IEEE, Dec. 1965, pp. 2117-2118.
Sprague, J. L., J. Lindmayer, R. Garnache and J. J. Casey, "Metal-Base Transistor Studies", 23rd Conference on Physical Electronics Applied MIT, Cambridge, Mass. 1963.
Lindmayer, Joseph, "The Metal-Gate Transistor", Proceedings of the IEEE, 1964, p. 1751.
Lindmayer, J. and Wigley, "Metal Gate Transistor", Fundamentals of Semiconductor Devices, pp. 458-460.
Von Muench, W., "Producing Semiconductor Devices by Oriented Lateral Overgrowth", IBM Technical Disclosure Bulletin, vol. 10, No. 10, Mar. 1968, pp. 1469-1470.
Nishizawa, J. and M. Watanabe, "A Semiconductor Device With High Re-Resistance Area", Patent Report of Bureau of Patents, Nov. 25, 1953.
Rose, A., "An Analysis of Gain-Bandwidth Limitations of Solid-State Triodes", RCA Rev., vol. 24, Dec. 1963, pp. 627-640.
Shockley, W., "The Path of the Conception of the Junction Transistor", IEEE Transactions on Electron Devices, vol. ED-23, No. 7, Jul. 1976, pp. 597-620.
Tausch, F. W. and A. G. Lapierre, III, "A Novel Crystal Growth Phenomenon: Single Crystal GaAs Overgrowth onto Silicon Dioxide", Journal of the Electrochemical Society, vol. 112, No. 7, Jul. 1965, pp. 706-709.
Yamaguchi, K. and H. Kodera, "Optimum Design of Triode-Like JFETR's by Two-Dimensional Computer Simultaion", IEEE Transistors on Electron Devices, vol. ED-24, No. 8, Aug. 1977, pp. 1061-1069.

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