Semiconductor element layout method employing process migration

Details Semiconductor element layout method employing process migration Semiconductor element layout method employing process migration

1994-11-04

1997-03-11

Teska, Kevin J.

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364488, 364489, 364490, 430 5, 430 22, 430311, 430315, 437 50, 437 47, 437 51, 437190, G06F 1500, G03F 900, H01L 2170

Patent

active

056108311

ABSTRACT:
A semiconductor element layout method carries out process migration to convert a first mask layout prepared for integrated circuits according to a first design rule into a second mask layout that follows a second design rule. The process migration selectively removes substrate contacts that are present between adjacent elements on the first mask layout.

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Dao et al., "A Compaction Method for Full Chip VLSI Layouts", 30th ACM/IEEE Design Automation Conference, (1993), pp. 407-412.

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