Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-01-07
2001-05-15
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S693000
Reexamination Certificate
active
06232655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor element having external connection terminals, a method of manufacturing the semiconductor element, and a semiconductor device equipped with the semiconductor elements and, more particularly, a semiconductor element, a method of manufacturing the semiconductor element, and a semiconductor device, capable of reducing a placement area of external connection terminals on an integrated circuit mounting surface.
2. Description of the Prior Art
In general, a semiconductor device comprises a semiconductor element and a package in which the semiconductor device is mounted. On a surface of the semiconductor element are formed external connection terminals (electrodes) which connect electrically an integrated circuit formed on the semiconductor element to an external device placed on the outside of the package. Lead wirings are provided on the package. The external connection terminals of the semiconductor element and the lead wirings are electrically connected indirectly via wires formed by means of wire bonding technique or directly by wireless bonding technique.
As shown in
FIG. 12
, an optical element
1
such as an image sensor, a solid state imaging device, etc. in the prior art includes at least a photo detector
3
and external connection terminals
5
disposed in the neighboring area of the photo detector
3
on its surface. The photo detector
3
can execute so-called photoelectric conversion to convert optical signals into electric signals. Though not shown, peripheral circuits such as a CCD (Charge Coupled Device) which can transfer sequentially the electric signals derived by photoelectric conversion by use of the photo detector
3
are disposed around the photo detector
3
. The external connection terminals
5
connect electrically the photo detector
3
and the external device (not shown).
As shown in
FIG. 13
, an optical device
10
comprise the optical element
1
and a package
12
in which the optical element
1
is mounted. A glass lid
14
which is able to transmit the optical signals is provided on the package
12
. The optical device
10
can be hermetic-sealed by the glass lid
14
and the package
12
.
As shown in
FIGS. 13 and 14
, the lead wirings
13
are formed in the outer periphery of the optical element
1
on the package
12
. In the case that the wire bonding is employed, the external connection terminals
5
of the optical element
1
and the lead wirings
13
are connected electrically by bonding wires
9
. The optical element
1
is bonded to the package
12
by die bonding technique.
With the high advance and complication of LSIs in recent years, there has been a tendency that the number of terminals required for the semiconductor element is increased. However, if the number of terminals are simply increased based on a layout rule for the external connection terminals on the semiconductor element in the prior art, an increase in an element area is brought about. In order to overcome this drawback, such a method can be considered that the increase in the element area should be avoided by reducing a distance between the external connection terminals respectively. In this case, the bonding technique with extremely high accuracy is requested since the distance between the external connection terminals must be narrowed rather than that in prior art.
FIG. 15
is a sectional view showing the wire bonding which is now applied to the optical element. The bonding wire
9
is pushed against the external connection terminal
5
by use of a capillary
15
and then bonded to the external connection terminal
5
in terms of ultrasonic vibration. However, in the optical element
1
shown in
FIG. 12
, the external connection terminals
5
are disposed closer to each other and in addition the photo detector
3
and the external connection terminal
5
are disposed closer to each other. As a result, there has been caused such a disadvantage that a part of a surface of the external connection terminal
5
is peeled off upon bonding and then such peelings fall to the photo detector
3
and then stick thereto as adhesive substance
16
. In addition, unless enough bonding accuracy can be achieved, the capillary
15
does not abut upon the external connection terminal
5
exactly, but upon a protection film coated on the surface of the optical element
1
. Therefore, there has been caused another disadvantage that a part of the protection film is peeled off and then such peeled films also fall to the photo detector
3
and then stick thereto as adhesive substance
16
.
As shown in FIG.
16
(A), in the case that, for example, the adhesive substance
16
falls to a pixel
3
c
out of a plurality of pixels
3
a
to
3
e
constituting the photo detector
3
, there are some cases where a white level signal which should be output properly from the pixel
3
c
is converted into a black level signal, as shown in FIG.
16
(B), when a light is incident into the photo detector
3
. As a consequence, proper signal output values cannot be output from the photo detector
3
.
In order to overcome the above disadvantages, a semiconductor element set forth in Patent Application Publication (KOKAI) 3-104246 has been proposed.
FIG. 17
is a view showing a configuration of the semiconductor element
1
a
in the prior art. In this semiconductor element
1
a
, the external connection terminals
5
are disposed on side surfaces of the semiconductor element
1
a
, so that an occupied area of the external connection terminals
5
on a surface of the semiconductor element
1
a
can be reduced, which results in reduction in the surface area of the semiconductor element
1
a
. In addition, if the semiconductor element set forth in the above Patent Application Publication (KOKAI) 3-104246 is applied to the above optical device
10
, there has not been caused the disadvantage due to the adhesive substance
16
generated during wire bonding since the photo detector
3
and the external connection terminals
5
of the optical element
1
are formed on different surfaces of the optical element
1
, as shown in FIG.
18
.
Nevertheless, in the above semiconductor element
1
a
shown in
FIG. 17
, the external connection terminals
5
can be formed on the side surfaces of the semiconductor element
1
a
, but the electrical measuring electrodes
17
used to execute the electrical measurement of the integrated circuit in the course of production process (wafer process) is required separately. The electrical measuring electrodes
17
are arranged on the surface of the semiconductor element
1
a
as the integrated circuit mounting surface. The electrical measuring electrodes
17
and the external connection terminals
5
are connected electrically by the wirings
18
respectively, so that the external connection terminals
5
are connected electrically to the not shown integrated circuit in the semiconductor element
1
a
via the wirings
18
and the electrical measuring electrodes
17
respectively. In the optical device
10
, the electrical measuring electrodes
17
as well as the photo detector
3
are arranged on the surface of the optical element
1
and the external connection terminals
5
are arranged on the side surfaces of the optical element
1
. The occupied areas of the electrical measuring electrodes
17
are small rather than those of the external connection terminals
5
. However, the occupied areas of the electrical measuring electrodes
17
are not so small as they can be neglected. For this reason, the element area of the optical element
1
cannot be sufficiently reduced because the electrical measuring electrodes
17
are required substantially as many as the external connection terminals
5
.
In addition, the increase in the element area of the optical element
1
results in an increase in size of the package
12
and therefore the optical device
10
is enlarged in size.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the above problems, and it is an object o
Cao Phat Xuan
Chaudhuri Olik
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor element having external connection terminals,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor element having external connection terminals,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor element having external connection terminals,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2442061