Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate
2002-06-18
2003-11-25
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With dam or vent for encapsulant
Reexamination Certificate
active
06653720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor electronic parts.
2. Description of Related Arts
Conventional semiconductor electronic parts has involved adhesive bonding a bare chip to the upper part of an island formed at an approximately central portion of a lead frame, connecting electrode pads formed on the bare chip to respective lead terminals (electrode terminals) formed at the peripheral edge of the lead frame via gold wires with wire bonding, and sealing the bare chip with a resin.
When the conventional semiconductor electronic parts having one bare chip placed on the upper part of the island of the lead frame and the plurality of lead terminals arranged around the bare chip were mounted on a printed wiring board, an area occupied by the semiconductor electronic parts was larger on the printed wiring board which caused hindrance in reducing the size of electronic equipment.
In these years, to achieve a high-density construction, so-called chip-on-chip type semiconductor electronic parts have been developed in which another bare chip is adhesive bonded to the upper part of the bare chip, the upper bare chip is connected to the lower bare chip with die-bonding, the electrode pads formed on the lower bare chip are connected to the respective lead terminals (the electrode terminals) via the gold wires with wire bonding and then both bare chips are sealed with a resin.
In the process of manufacturing the chip-on-chip type semiconductor electronic parts, during adhesive bonding the upper bare chip to the upper part of the lower bare chip, bumps formed on the upper face of the lower bare chip and bumps formed on the lower face of the upper bare chip were connected together with die-bonding (a die-bonding process) and then an adhesive was injected into a gap formed between both bare chips by a dispenser (an underfill process). The upper and lower bare chips were thereby adhesive bonded to each other.
The developed semiconductor electronic parts having a high-density construction included a flip-chip mounting, where the bare chip was connected to the printed wiring board with die-bonding and the adhesive is injected into the gap formed between the bare chip and the printed wiring board (an underfill process) and the bare chip was sealed with the resin, and a chip-size package (CSP), where the bare chip was adhesive bonded to a film (an underfill process), the electrode pads on the film were connected to the respective electrode pads on the bare chip via inner wires and then the electrode pads on the film were connected to the respective electrode pads on the printed wiring board via outer wires.
Concerning the conventional semiconductor electronic parts, described above, in the underfill process of bonding the bare chip to the upper part of the base (the bare chip, the printed wiring board, the film or others) with the adhesive and sealing the gap formed between the upper face of the base and the lower face of the bare chip, a less amount of adhesive to be injected has produced bubbles inside without completely sealing the gap between the base and the bare chip. The bubbles might have been thermally expanded in a soldering process to give damage to the bare chip. Therefore, a sufficient amount of adhesive should have been injected between the base and the bare chip.
If a larger amount of adhesive, than a proper amount, has been injected between the base and the bare chip so that a sufficient amount of adhesive can be injected therebetween in the underfill process, the adhesive injected between the base and the bare chip has overflowed to the outside of the bare chip and the overflowing adhesive has flowed into the upper parts of the electrode pads formed on the upper face of the base, with the result that the electrode pads might have been covered with the adhesive.
The deposition of the adhesive on the electrode pads in the underfill process might have precluded the bonding of the wires to the electrode pads in the following wire bonding process of connecting the electrode pads to the respective electrode terminals with the wires or might have caused poor continuity between the electrode pad and the wire.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, semiconductor electronic parts comprise a plurality of electrode pads formed on the surface of a base and adapted to be connected to respective electrode terminals and a bare chip adhesive bonded to the surface of the base, wherein adhesive flow-in preventing means is provided between the bare chip and each of the electrode pads for preventing an adhesive for adhesive bonding the bare chip to the base from flowing into the electrode pads.
According to another aspect of the present invention, the adhesive flow-in preventing means is a peripheral wall so formed on the surface of the base as to encircle the bare chip.
According to another aspect of the present invention, an inlet for injection of the adhesive is formed in the peripheral wall.
According to another aspect of the present invention, a plurality of grooves are formed in the surface of the base or in the reverse of the bare chip for admitting the adhesive.
According to another aspect of the present invention, a chip-on-chip arrangement is constructed by forming the base with the bare chip.
REFERENCES:
patent: 5278446 (1994-01-01), Nagaraj et al.
patent: 5729050 (1998-03-01), Kim
patent: 6239480 (2001-05-01), MacPherson et al.
patent: 6391682 (2002-05-01), Tsai et al.
patent: 02238999 (1990-09-01), None
Jordan and Hamburg LLP
Rohm & Co., Ltd.
Wilson Allan R.
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