Semiconductor dynamic memory device with metal-level selection o

Details Semiconductor dynamic memory device with metal-level selection o Semiconductor dynamic memory device with metal-level selection o

1989-08-14

1991-03-19

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

3652385, 36523009, 36518911, 365193, G11C 800, G11C 700

Patent

active

050016733

ABSTRACT:
A semiconductor dynamic memory device contains circuitry for implementing either page mode or nibble mode access using a selected conductor connection. A clock voltage used in column decoding and outputting is coupled either from the column strobe or the CAS input by a conductor so that the clock voltage is rendered either dependent upon or independent from the cycling of the column strobe.

REFERENCES:
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patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4586167 (1986-04-01), Fujishima et al.
patent: 4618946 (1986-10-01), Little et al.
patent: 4618947 (1986-10-01), Tran et al.
patent: 4800530 (1989-01-01), Itoh et al.
patent: 4807192 (1989-02-01), Nakano et al.
patent: 4876671 (1989-10-01), Norwood et al.
K. Shimotori et al., "A 100ns 256K DRAM with Page Nibble Mode", Digest of Technical Papers, 1983 IEEE International Solid-State Circuits Conference, pp. 228-229.

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