Semiconductor dynamic memory device with metal-level selection o

Details Semiconductor dynamic memory device with metal-level selection o Semiconductor dynamic memory device with metal-level selection o

1989-04-06

1989-10-24

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

3652385, 36523009, 36518911, 365193, G11C 800, G11C 700

Patent

active

048766712

ABSTRACT:
A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.

REFERENCES:
patent: 4422160 (1983-12-01), Watanabe
patent: 4510602 (1985-04-01), Engdahl et al.
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4586167 (1986-04-01), Fujishima et al.
patent: 4618946 (1986-10-01), Little et al.
patent: 4618947 (1986-10-01), Tran et al.

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