Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-10-17
2002-04-02
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S109000, C327S534000, C326S036000, C326S087000
Reexamination Certificate
active
06366141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit, and particularly to a body bias variable driver circuit for implementing operation at a low source voltage.
This application is a counterpart of Japanese Patent Application, Serial Number 006093/2000, filed Jan. 11, 2000, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A circuit disclosed in the following reference has heretofore been proposed as an SOI (Silicon On Insulator). driver circuit for controlling a substrate voltage.
“Body Bias Variable SOI-CMOS Driver Circuit”, by Yoshiki Wada et al; Mitsubishi Electric Corp., S. (Signal)-L.(Learning) Technical Report of IEICE, ICD97-45, p. 23-29, 1997
A description will now be made of the body bias variable SOI-CMOS driver circuit (hereinafter abbreviated as “driver circuit” disclosed in the above-described reference.
FIG. 8
is a circuit diagram of the driver circuit disclosed in the above-described reference. The driver circuit comprises an inverter circuit A, a substrate voltage supply circuit B and an inverter circuit C. The substrate voltage supply circuit B is electrically connected to the inverter circuit A and the inverter circuit C.
The inverter circuit A comprises a PMOS transistor
802
and an NMOS transistor
803
.
The PMOS transistor and NMOS transistor will now be described. The PMOS transistor is an abbreviation for ‘P channel MOS transistor’ and is comprised of a control electrode, a first electrode, and a second electrode. The first electrode of the PMOS transistor serves as a source or drain electrode, and the second electrode thereof serves as a drain or source electrode. When a reference voltage GND (also called “ground voltage GND”; hereinafter abbreviated as “voltage GND” is applied to the control electrode of the PMOS transistor, the PMOS transistor is brought to a conducting state. On the other hand, when a source voltage V
DD
(also called “drive voltage V
DD
”; hereinafter abbreviated as “voltage V
DD
” is applied to the control electrode of the PMOS transistor, the PMOS transistor is brought to a non-conducting state. Next, the NMOS transistor is an abbreviation for ‘N channel MOS transistor’ and comprises a control electrode, a first electrode and a second electrode. The first electrode of the NMOS transistor serves as a source or drain electrode, and the second electrode thereof serves as a drain or source electrode. When the voltage V
DD
is applied to the control electrode of the NMOS transistor,the NMOS transistor is brought to the conducting state. On the other hand, when the voltage GND is applied to the control electrode of the NMOS transistor, the NMOS transistor is brought to the non-conducting state. Incidentally, a period during which each of the PMOS transistor and the NMOS transistor changes from the non-conducting state to the conducting state, is called an “active period” and a period other than that is called a “static period” in the subsequent description.
In the inverter circuit A, the control electrode of the PMOS transistor
802
is electrically connected to a node
801
, the first electrode thereof is supplied with the voltage V
DD
, and the second electrode thereof is electrically connected to a node
804
. Further, the control electrode of the NMOS transistor
803
is electrically connected to the node
801
, the first electrode thereof is supplied with the voltage GND, and the second electrode thereof is electrically connected to the node
804
.
The substrate voltage supply circuit B comprises two PMOS transistors
805
and
806
and two NMOS transistors
807
and
808
.
The voltage GND is applied to a control electrode of the PMOS transistor
805
, the voltage V
DD
is applied to a first electrode thereof. Further, a second electrode of the PMOS transistor
805
is electrically connected to a node BP. In the substrate voltage supply circuit B, the voltage GND is always applied to the control electrode of the PMOS transistor
805
so that the PMOS transistor
805
is always kept in conduction. Thus, the PMOS transistor
805
is used as resistance means interposed between the node BP and the voltage V
DD
. A control electrode of the PMOS transistor
806
is electrically connected to a node
809
, a first electrode thereof is electrically connected to the node BP, and a second electrode thereof is electrically connected to the node
804
. A substrate for the PMOS transistor
806
and the node BP are now connected to each other, whereby the voltage applied to the. substrate of the PMOS transistor
806
depends on a voltage applied to the node BP.
The voltage V
DD
is applied to a control electrode of the NMOS transistor
807
, a first electrode thereof is supplied with the voltage GND, and a second electrode thereof is electrically connected to a node BN.
In the substrate voltage supply circuit B, the voltage V
DD
is applied to the control electrode of the NMOS transistor
807
at all times so that the NMOS transistor
807
is always kept in conduction. Thus, the NMOS transistor
807
is utilized as resistance means interposed between the node BN and the voltage GND. A control electrode of the NMOS transistor
808
is electrically connected to the node
809
, a first electrode thereof is electrically connected to the node BN, and a second electrode thereof is electrically connected to the node
804
. A substrate for the NMOS transistor
808
is electrically connected to the node BN here, so that a voltage applied to the substrate of the NMOS transistor
808
depends on the voltage applied to the node BN.
The inverter circuit C comprises a PMOS transistor
810
and an NMOS transistor
811
. A control electrode of the PMOS transistor
810
is electrically connected to the node
804
, a first electrode thereof is supplied with the voltage V
DD
, and a second electrode thereof is electrically connected to the node
809
. Further, a control electrode of the NMOS transistor
811
is electrically connected to the node
804
, a first electrode thereof is supplied with the voltage GND, and a second electrode thereof is electrically connected to the node
809
. A substrate for the PMOS transistor
810
is electrically connected to the node BP, whereas a substrate for the NMOS transistor
811
is electrically connected to the node BN.
The operation of the driver circuit described in the above-described reference will next be explained with reference to
FIGS. 8 and 9
.
FIG. 9
shows the result of simulation of the driver circuit. FIG.
9
(
a
) is a timing chart showing waveforms at the nodes
804
and
809
. FIG.
9
(
b
) is a timing chart showing waveforms at the nodes BP and BN.
Now consider where the voltage GND is first applied to the node
801
at a time T
1
. In doing so, the NMOS transistor
803
is brought into non-conduction and the PMOS transistor
802
is brought into conduction. Thus, the node
804
is brought to the voltage V
DD
since the PMOS transistor
802
is kept in conduction.
Since the voltage V
DD
is applied to the node
804
, the PMOS transistor
810
is brought into non-conduction and the NMOS transistor
811
is brought into conduction. Thus, since the NMOS transistor
811
is kept in conduction, the node
809
assumes the voltage GND.
Since the voltage GND is applied to the node
809
, the NMOS transistor
808
is brought to the non-conducting state and the PMOS transistor
806
is brought to the conducting state. Since the NMOS transistor
808
is kept in non-conduction, the node BN is maintained at the voltage GND. Since the NMOS transistor
807
is kept in conduction, the voltage GND is applied to the substrates for the NMOS transistor
808
and the NMOS transistor
811
. On the other hand, since the PMOS transistor
806
is kept in conduction and the PMOS transistor
805
is kept in conduction, the voltage V
DD
is applied to the node
804
. Incidentally, since the PMOS transistor
805
is kept in conduction, the voltage V
DD
is applied to the substrates for the PMOS transistors
806
and
810
Assume that
Chiba Tadashi
Morikawa Koichi
Callahan Timothy P.
Luu An T.
Oki Electric Industry CO Ltd.
Rabin & Berdo P.C.
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