Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-09-29
2003-07-22
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Reexamination Certificate
active
06597349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor display device for displaying information, such as a picture, by means of pixels arranged in matrix.
2. Description of the Related Art
In recent years, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, such as a thin film transistor (TFT), has been rapidly developed. The reason is that a demand for an active matrix type liquid crystal display device (liquid crystal panel) has been increased.
The active matrix type liquid crystal panel is structured such that a TFT is disposed for each of several tens to several millions of pixel regions arranged in matrix, and an electric charge going in and out of the respective pixel electrodes is controlled by the switching function of the TFT.
Among them, attention comes to be paid to a digital gradation system active matrix liquid crystal display device capable of being driven at high speed.
As shown in
FIG. 1
, a conventional digital gradation system active matrix liquid crystal display device includes a source signal line side shift register
101
, a digital decoder
102
, latch circuits
103
(LAT
1
), latch circuits
104
(LAT
2
), a latch pulse line
105
, D/A conversion circuits
106
, source signal lines
107
, a gate signal line side shift register
108
, gate signal lines (scanning line)
109
, pixel TFTs
110
, and the like.
Digital gradation signals supplied to address lines
1
to
4
of the digital decoder
102
are written in the LAT
1
by timing signals from the source signal line side shift register
101
.
A time in which writing of the digital gradation signals into the LAT
1
group is roughly ended, is referred to as one line period. That is, one line period is a time interval between the start point of writing of a gradation signal from the digital decoder
102
into the leftmost LAT
1
in FIG.
1
and the end point of writing of a gradation signal from the digital decoder
102
into the rightmost LAT
1
.
After the writing of the gradation signals into the LAT
1
group is ended, a latch pulse flows to the latch pulse line
105
synchronously with the operation timing of the shift register, so that the gradation signals written in the memory
1
group are transmitted all at once into the LAT
2
group.
Into the LAT
1
group which have finished transmission of the gradation signals into the LAT
2
group, writing of gradation signals supplied to the digital decoder
102
is again sequentially carried out by a signal from the source signal line side shift register
101
.
In the second one line period, according to the gradation signals transmitted to the LAT
2
group synchronously with the start of the second one line period, gradation voltages are selected by the D/A conversion circuits (digital/analog conversion circuits)
106
.
The selected gradation voltages are supplied to the corresponding source signal lines in one line period.
By repeating the above-mentioned operation, images are supplied to the entire of the pixel portions of the liquid crystal display device.
However, in the case of the foregoing digital gradation liquid crystal display device, the area of the D/A conversion circuit is actually rather large as compared with other circuits, which hinders miniaturization of the liquid crystal display device requested in recent years.
In recent years, with the rapid increase of the amount of information to be treated, it has been designed to increase the display capacity (display resolution) and to make display resolution fine. However, with the increase of the display capacity, the number of D/A conversion circuits is also increased, so that reduction of an area of a driving circuit portion is earnestly desired.
Here, examples of generally used display resolution of a computer will be shown below with the number of pixels and the name of standard.
Number of pixels (Horizontal×Vertical): Name of standard
640×400: EGA
640×480: VGA
800×600: SVGA
1024×768: XGA
1280×1024: SXGA
For example, in the case where the XGA standard (1024×768 pixels) is cited as an example, in the foregoing driving circuit, a D/A converter is required for each of 1024 signal lines.
Recently, also in the field of a personal computer, since software for causing a plurality of presentations with different characters to be shown on a display has come into wide use, a display device corresponding to the XGA or SXGA standard with resolution higher than the VGA or SVGA standard becomes common.
Moreover, the above-mentioned liquid crystal display device having high resolution comes to be used also as display of a television signal other than display of a data signal in a personal computer.
In recent years, in order to realize a beautiful picture quality as in a high definition TV (HDTV) or an extended definition TV (EDTV), image data for one picture becomes several times that of a conventional TV. Moreover, since the easiness of viewing is improved and it becomes possible to display a plurality of pictures on one display device by enlarging a screen, a large screen and high gradation comes to be increasingly required.
As the standard of display resolution of a TV (ATV) for a future digital broadcast, the standard of 1920×1080 pixels is promising, and the reduction of an area of a driving circuit portion is rapidly demanded.
However, as described above, since an occupied area of a D/A conversion circuit is large, as the number of pixels increases, the area of the driving circuit portion becomes remarkably large, which hinders the miniaturization of a liquid crystal display device.
SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing problems, and an object of the present invention is therefore to provide a small semiconductor display device, especially a liquid crystal display device by decreasing an occupied area of D/A conversion circuits in a driving circuit portion.
According to an aspect of the present invention, a semiconductor display device comprises a D/A conversion circuit portion including a plurality of D/A conversion circuits, and each of the plurality of D/A conversion circuits sequentially makes analog conversion of digital gradation signals supplied from a memory circuit. The above object is achieved by this device.
The memory circuit may include a plurality of latch circuits.
According to another aspect of the present invention, a semiconductor display device comprises a memory circuit for storing m x-bit digital gradation signals (m and x are natural numbers), and a D/A conversion circuit portion for making analog conversion of the m x-bit digital gradation signals supplied from the memory circuit and for supplying analog signals to m source signal lines, the D/A conversion circuit portion includes n D/A conversion circuits (n is a natural number), and each of the n D/A conversion circuits sequentially makes analog conversion of the m
x-bit digital gradation signals to supply converted signals to corresponding m
source signal lines. The above object is achieved by this device.
The memory circuit may include a plurality of latch circuits.
According to still another aspect of the present invention, a method of driving a semiconductor display device comprises the steps of storing m x-bit digital gradation signals (m and x are natural numbers) for one line, and sequentially making analog conversion of the m
x-bit digital gradation signals in one line period by each of n D/A conversion circuits (n is a natural number) to transmit converted signals to corresponding m
source signal lines. The above object is achieved by this method.
According to yet another aspect of the present invention, a method of driving a semiconductor display device comprises the steps of sampling and storing m x-bit digital gradation signals by a timing signal from a shift register (m and x are natural numbers), and sequentially making analog conversion of the m
x-bit digital gradation signals by
Azami Munehiro
Koyama Jun
Osame Mitsuaki
Hjerpe Richard
Laneau Ronald
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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