Semiconductor diodes with fin structure

Details Semiconductor diodes with fin structure Semiconductor diodes with fin structure

2003-03-25

2004-12-28

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Tunneling pn junction device

C257S594000, C257S623000, C257S624000

Reexamination Certificate

active

06835967

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of semiconductor devices, and more specifically, to a semiconductor diode device for electrostatic discharge protection in advanced complementary metal-oxide-semiconductor (CMOS) technologies. The semiconductor diode provided by this invention is compatible with the fabrication process of advanced transistors such as multiple-gate-transistors.
BACKGROUND OF THE INVENTION
Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects.
When the gate length is scaled down into the sub-50 nanometer (nm) regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. For device scaling well into the sub-50 nm regime, a promising approach to controlling short-channel effects is to use an alternative device structure with multiple-gates, such as the double-gate structure and triple-gate structures. The multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
FIG. 1A
shows an enlarged, cross-sectional view of a conventional diode structure
10
fabricated on bulk silicon substrate
12
.
FIG. 1B
shows an enlarged, cross-sectional view of a conventional diode structure
20
fabricated on an silicon-on-insulator (SOI) wafer
22
, also known as a lateral unidirectional bipolar insulated gate type transistor (or lubistor). In both these structures, the n+ and p+ regions
14
,
16
are formed on the opposite sides of the polysilicon (poly-Si) gate stack
18
. The n+ and p+ regions
14
,
16
in the substrate
12
,
22
are used as the two terminals of the diode. The poly-Si gate stack
18
in the structures of
FIGS. 1A and 1B
may be connected to the cathode (n+ region of the poly-Si), for example.
Most of the work on advanced device structures such as the multiple-gate transistors focus on the transistor structure and method of fabrication. There is little or no work on the provision of electrostatic discharge protection for these nanoscale devices. Transistor size reduction has resulted in the thinning of insulator layers such as the gate dielectric layer. These thinner dielectric layers fail at lower voltages. Consequently, device scaling increases circuit sensitivity to voltage stress, electrical overstress (EOS), and electrostatic discharge (ESD). These types of failures are a major concern in advanced semiconductor technology. This is especially true for integrated circuit (IC) chips that interface with other chips or signals with voltages above that of the IC chip itself. IC chips usually include protection devices or diodes in interface circuits to provide the IC chip with added ESD protection. U.S. Pat. No. 5,629,544, entitled “Semiconductor diode with silicide films and trench isolation”, issued to Voldman et al, teaches the use of diode structures bound by polysilicon for bulk silicon and silicon-on-insulator (SOI) MOSFET applications. U.S. Pat. Nos. 6,015,993 and 6,232,163B1, both issued to Voldman et al, discuss a high voltage tolerant diode structure for mixed-voltage and mixed signal and analog/digital applications. These prior arts are applicable to bulk and SOI transistor technologies. For future advanced technologies that employ device structures such as the multiple-gate transistors, new electrostatic discharge protection elements that are more advanced with improved characteristics should be used to provide superior voltage protection for nanoscale devices.
Semiconductor diodes used for ESD protection should have low series resistance, low sub-threshold leakage, and low reverse leakage. The series resistance is the most important factor for achieving good ESD performance. ESD protection levels improves with reduction in diode series resistance. The series resistance characteristic is especially important in a mixed voltage environment where diode strings are used and where the series resistance of each diode add to degrade ESD performance. Diode resistance is largely determined by the size of the diode, the resistivity of the material constituting the diode body, the distance of the current path, and the resistance of silicide films or contacts to n+ and p+ diffusions. Thus, a wider diode with a lower body resistivity, a shorter current path, and silicided films and contacts provide a lower diode series resistance.
It is therefore an object of the present invention to provide a semiconductor diode for electrostatic discharge protection.
It is another object of the present invention to provide a semiconductor diode that is compatible with a fabrication process of advanced transistors such as multiple-gate transistors.
It is a further object of the present invention to provide a semiconductor diode equipped with contacts on the sidewalls of the silicon body.
It is another further object of the present invention to provide a semiconductor diode with improved area efficiency.
It is still another object of the present invention to provide a n+/p+ tunnel diode with a fin structure.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor diode structure and a semiconductor diode string are provided.
In a preferred embodiment, a semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting
In the semiconductor diode structure, the semiconducting material may include silicon, or may include silicon and germanium, or may include a compound semiconductor. The substrate may include a layer of an insulating material, wherein the insulating material may be silicon oxide, or may be a dielectric selected from silicon nitride and aluminum oxide. The first doping type may be formed by using n-type dopant selected from phosphorus, arsenic and antimony. The second heavily-doped region of the second doping type may be formed by using p-typed dopant selected from the group boron and indium. The first and the second conductor may be formed of a material such as tungsten or copper, or may be formed of a metallic nitride of titanium nitride or tantalum nitride, or may be formed of a heavily-doped semiconducting material, or may be formed of p+ doped polysilicon. The first and the second conductor may further include a first conductive layer underlying a second conductive layer, wherein the first conductive layer may be titanium nitride and the second conductive layer may be tungsten. The fin may have a width between about 50 angstroms and about 5000 angstroms, and a height greater tha

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