Semiconductor die with process variation compensated...

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Reexamination Certificate

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C365S225700, C327S538000, C324S765010

Reexamination Certificate

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11187431

ABSTRACT:
A semiconductor die includes at least one process monitoring circuit for evaluating at least one process parameter of the semiconductor die. The at least one process monitoring circuit can include a first group of process monitoring circuits for monitoring NFET speed and a second group of process monitoring circuits for monitoring PFET speed. The process monitoring circuits can be distributed at the corners of the semiconductor die. The semiconductor die further includes a voltage control circuit configured to store optimum voltage information corresponding to the at least one process parameter. The voltage control circuit is further configured to selectively provide the optimum voltage information to a system power supply. The voltage control circuit includes a calculated optimum voltage register that stores the optimum voltage information corresponding to the at least one process parameter.

REFERENCES:
patent: 6211727 (2001-04-01), Carobolante
patent: 6897674 (2005-05-01), Braceras et al.
patent: 7060566 (2006-06-01), Vogelsang
patent: 2005/0162181 (2005-07-01), Braceras et al.

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