Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-07-27
2003-04-01
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S113000, C438S665000, C438S459000, C438S964000, C257S739000
Reexamination Certificate
active
06541352
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to the art of semiconductor device manufacturing and more particularly to methods for fabricating semiconductor devices having contoured bottom surfaces.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor devices, such as integrated circuits (ICs), multiple devices and interconnections (e.g., circuits) are formed on a semiconductor wafer and then separated or singulated into individual parts or dies. This allows cost savings and reduced handling compared to forming the devices individually. The individual devices are located within corresponding die areas on the wafer with sufficient spacing provided between adjacent devices for subsequent separation operations and the manufacturing tolerances associated therewith. Typically, the devices are oriented in grid style on the wafer, with rows and columns of devices located on the top or front side of the wafer, wherein the devices are formed by multi-step processing involving selective deposition, removal, and/or doping of areas on the wafer surface to build electrical devices (e.g., transistors, diodes, resistors, capacitors, etc.) and connections therebetween.
Such devices may include integrated circuits, micro electro-mechanical structure (MEMS) devices, optical, opto-electronic, and other types of circuits. Photo-lithographic techniques are commonly employed in order to produce high density devices having hundreds, thousands, or millions of components with very small device feature sizes. Once the devices are created, the individual circuits on the wafer may be tested, after which the individual device dies are separated.
The wafers are typically back-ground through chemical mechanical planarization (CMP) or other material removal techniques, prior to die separation, wherein material is removed from the bottom or back side of the wafer, leaving a smooth bottom surface. The back-grinding is employed to provide dies having a desired final thickness, depending on the target application for which the dies are being produced. Separation of the individual tested dies from the wafer assembly is conventionally done by sawing or otherwise mechanically creating scribe lines such as channels or trenches extending completely through the wafer from the top side, which are located in the spacing or gaps between adjacent devices or die areas. In order to maintain the die in the row and column grid configuration, as well as to mechanically support the die during separation, a tape is applied to the bottom surface (and sometimes also to the top surface) of the wafer prior to the final separation step.
Once the individual dies are physically separated from one another, the dies can be removed from the tape, or alternatively, rows of taped components can be packaged for later provision to pick and place machinery. The semiconductor dies may then be assembled into integrated circuit chips, or may alternatively be secured directly onto printed circuit boards (PCBs), substrates, carriers, suspensions, or other mountings, wherein electrical connections are made to one or more electrically conductive bonding pads on the dies.
When employed in an integrated circuit chip, the semiconductor die is mounted onto a lead frame and wires are connected between lead frame leads and corresponding bonding pads on the die using a technique known as wire bonding. Wire bonding uses fine aluminum or gold wires (e.g., 25 &mgr;m in diameter), which are bound to the bonding pads through thermocompression bonding or ultrasonic bonding. Thermocompression bonding involves heating the die and the wire to a high temperature (e.g., about 250 degrees C.), and heating the tip of the wire to form a ball. A holding tool then forces the wire into contact with the bonding pad on the die. The wire adheres to the pad due to the combination of heat and pressure from the tool. The tool is then lifted up and moved in an arc to the appropriate position on the lead frame, while dispensing wire as required, where the process is repeated to bond the wire to the appropriate lead on the lead frame, except that a ball is not formed.
Ultrasonic bonding is sometimes used when the device cannot or should not be heated. The wire and bonding surface (e.g., a bonding pad on the die or a lead on the lead frame) are brought together by the tool, and ultrasonic vibration is used to compress the surfaces together to achieve the desired bond. Once the pads are appropriately connected to the lead frame leads, the lead frame is encapsulated in a ceramic or plastic integrated circuit package (e.g., with portions of the leads externally exposed), which may then be assembled onto a PCB by soldering the exposed leads onto corresponding conductive pads on the board.
Recently, Flip-Chip technology has become popular, wherein an individual semiconductor die is mounted directly to a substrate, PCB, suspension, flex-circuit or the like. Bumps (e.g., solder bumps, plated bumps, gold stud bumps, adhesive bumps, or the like) are added to the bonding pads of the die using a process known as bumping. For example, gold stud bumps are formed through a modified wire bonding technique. This technique makes a gold ball for wire bonding by melting the end of a gold wire to form a sphere. The gold ball is attached to the chip bond pad as the first part of a wire bond. To form gold bumps instead of wire bonds, wire bonders are modified to break off the wire after attaching the ball to the chip bond pad. The resulting gold ball, or “stud bump” remains on the bond pad and provides a permanent connection through the aluminum oxide to the underlying metal.
The bumping step is usually performed during wafer processing prior to separation of the individual die from the wafer. However, the gold stud bump process is applicable to individual single dies or to wafers. With stud bumps attached, the die or chip is then “flipped” over, with the bonding pads facing downward, and the bumps are attached to corresponding pads on the board using ultrasonic bonding techniques (hence the name “Flip-Chip”). This is typically done by locating the die face-down on the circuit board, and engaging the backside of the chip with an ultrasonic tool. Ultrasonic energy is then applied to the die, whereby an electrical and mechanical bond is formed between the bumps on the die, and the corresponding pads on the circuit board.
Such Flip-Chip applications have numerous advantages, including shorter circuit connections, lower noise susceptibility, and higher component density. Accordingly, Flip-Chip technology (sometimes referred to as direct chip attach (DCA) or chip-on-board) has been successfully employed in a variety of applications, including electronic watches, wireless telephones, pagers, high-speed microprocessors, hand-held and lap-top computers. Another important application where chips or semiconductor dies are mounted directly onto a circuit is in hard disk drives, wherein all or part of a pre-amp circuit associated with a read-write head is mounted onto a flexible circuit or suspension located just above the rotating disk media using chip-on-suspension (COS) techniques. Such a pre-amp circuit may be formed in a small, ultra-thin die (e.g., the die may need to be thin, in order to clear the rotating disk), which is mounted directly onto the suspension for electrically conditioning signals to or from the read-write head. The physical size of the suspension circuit calls for die profiles on the order of 1000 to 2000 &mgr;m, and thickness on the order of about 125 &mgr;m.
However, several problems arise in this and other applications, which conventional die fabrication and separation techniques either fail to adequately address, or may even exacerbate. One problem with existing saw cutting and other mechanical die separation techniques is wasted wafer space. Conventional spacing between adjacent die areas in a wafer is about 100 &mgr;m or more, to accommodate saw blade widths (e.g., about 25 &mgr;m or more), and the alignment inaccuracies associated with such mechanical cutting op
Brady W. James
Nguyen Khiem
Swayze, Jr. W. Daniel
LandOfFree
Semiconductor die with contoured bottom surface and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor die with contoured bottom surface and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor die with contoured bottom surface and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3041496