Semiconductor die metal layout for flip chip packaging

Details Semiconductor die metal layout for flip chip packaging Semiconductor die metal layout for flip chip packaging

1997-11-03

2000-09-12

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257738, 257778, 22818022, H01L 2348, H01L 2352, H01L 2940

Patent

active

061181803

ABSTRACT:
Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

REFERENCES:
patent: 5162264 (1992-11-01), Haug et al.
patent: 5220199 (1993-06-01), Owada et al.
patent: 5726501 (1998-03-01), Matsubara

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