Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2006-06-27
2006-06-27
Thai, Luan (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S635000, C257S632000, C257S638000, C257S643000
Reexamination Certificate
active
07067901
ABSTRACT:
A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.
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Farnworth Warren M.
Wood Alan G.
Micro)n Technology, Inc.
Thai Luan
TraskBritt
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