Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2006-10-03
2006-10-03
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S696000, C257S684000, C257S673000, C257S686000, C257S685000, C257S690000, C257S691000, C257S666000, C257S784000, C257S786000, C257S787000, C257S777000, C361S777000, C174S02200R, C174S257000, C174S050510, C174S050510
Reexamination Certificate
active
07115984
ABSTRACT:
A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.
REFERENCES:
patent: 4956694 (1990-09-01), Eide
patent: 5138115 (1992-08-01), Lam
patent: 5266833 (1993-11-01), Capps
patent: 5313096 (1994-05-01), Eide
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5502667 (1996-03-01), Bertin et al.
patent: 5541450 (1996-07-01), Jones et al.
patent: 5639695 (1997-06-01), Jones et al.
patent: 5723901 (1998-03-01), Katsumata
patent: 5752182 (1998-05-01), Nakatsuka et al.
patent: 5834162 (1998-11-01), Malba
patent: 5925924 (1999-07-01), Cronin et al.
patent: 5986209 (1999-11-01), Tandy
patent: 6004867 (1999-12-01), Kim et al.
patent: 6034438 (2000-03-01), Petersen
patent: 6072236 (2000-06-01), Akram et al.
patent: 6228684 (2001-05-01), Maruyama
patent: 6252300 (2001-06-01), Hsuan et al.
patent: 6323546 (2001-11-01), Hsuan et al.
patent: 6335225 (2002-01-01), Doan
patent: 6352923 (2002-03-01), Hsuan et al.
patent: 6358833 (2002-03-01), Akram et al.
patent: 6379982 (2002-04-01), Ahn et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6461956 (2002-10-01), Hsuan et al.
patent: 6521485 (2003-02-01), Su et al.
patent: 6521995 (2003-02-01), Akram et al.
patent: 6552426 (2003-04-01), Ishio et al.
patent: 6582992 (2003-06-01), Poo et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6656827 (2003-12-01), Tsao et al.
patent: 6710454 (2004-03-01), Boon
patent: 6841418 (2005-01-01), Jeung et al.
patent: 6849802 (2005-02-01), Song et al.
patent: 6855572 (2005-02-01), Jeung et al.
patent: 6856023 (2005-02-01), Muta et al.
patent: 6876061 (2005-04-01), Zandman et al.
patent: 2001/0009300 (2001-07-01), Sugimura
patent: 2001/0042901 (2001-11-01), Maruyama
patent: 2002/0017398 (2002-02-01), Hacke et al.
patent: 2002/0079567 (2002-06-01), Lo et al.
patent: 2003/0080398 (2003-05-01), Badehi
patent: 2003/0102160 (2003-06-01), Gaudiello et al.
patent: 2003/0134453 (2003-07-01), Prabhu et al.
patent: 2003/0162326 (2003-08-01), Tsubosaki et al.
patent: 2003/0230802 (2003-12-01), Poo et al.
patent: 2003/0232482 (2003-12-01), Poo et al.
patent: 2004/0140573 (2004-07-01), Pu et al.
patent: 2004/0156177 (2004-08-01), Higashitani
patent: 2004/0251525 (2004-12-01), Zilber et al.
patent: 59-27549 (1984-02-01), None
patent: 59-43556 (1984-03-01), None
patent: 63-232342 (1988-09-01), None
patent: 5-75014 (1993-03-01), None
patent: 6-97225 (1995-04-01), None
patent: 2001-44361 (2001-02-01), None
patent: 2001-210521 (2001-08-01), None
patent: 2003-8066 (2003-01-01), None
NN81055595: Edge Mounted MLC Packaging Scheme. May 1981; IBM Technical Disclosure Buletin, May 1981 US: vol. 23, Issue # 12, p. # 5595-5598; Publication Date: May 1, 1981.
Australian Search Report, Apr. 15, 2005, 5 pages.
U.S. Appl. No. 10/717,421, filed Nov. 19, 2003.
Jeung Boon Suan
Kwang Chua Swee
Loo Neo Yong
Poo Chia Yong
Waf Low Siu
Micro)n Technology, Inc.
TraskBritt
Williams Alexander Oscar
LandOfFree
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