Semiconductor devices including fuses and multiple...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257S701000, C257S528000, C257S758000, C257S760000

Reexamination Certificate

active

06750529

ABSTRACT:

Applicant claims priority in and hereby incorporates by reference Japanese Application No. 2001-224689, filed Jul. 25, 2001, in its entirety. Applicant hereby incorporates by reference U.S. application Ser. No. 10/202,063, filed Jul. 25, 2002, in its entirety. Applicant hereby incorporates by reference U.S. application Ser. No. 10/202,028, filed Jul. 25, 2002, in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor devices including fuses, and includes semiconductor devices including fuses that may be fused by irradiation of a laser beam.
RELATED ART
Currently, replacement circuits are built in semiconductor devices in order to substitute for circuits that might become defective due to deficiencies that could occur during the manufacturing process. For example, in the case of a semiconductor memory device, since many of the deficiencies that occur during the manufacturing process would occur in its memory section, multiple redundant memory cells in units of word lines or bit lines are generally disposed therein. A redundant circuit controls the redundant memory cells. When a deficient element is generated in one chip that forms a semiconductor device, the redundant circuit provides a function to switch the deficient element to a normal element by irradiating a laser beam to a fuse element having an address corresponding to the deficient element to thereby fuse (break) the fuse element.
Due to demands in recent years in higher integration of semiconductor devices, memories have been further miniaturized. In connection with this trend, fuse elements themselves have also been miniaturized. Reliability of the fuse elements affects the production yield of semiconductor memory devices, and therefore highly reliable fusing of fuse elements is desired. Improvements in the reliability in fusing fuse elements can improve the production yield of semiconductor devices.
SUMMARY
Certain embodiments relate to a semiconductor device including a plurality of fuses arranged at a specified pitch, wherein the fuses are adapted to be fused by irradiation of a laser beam. The device also includes a first insulation layer embedded between adjacent ones of the fuses, and a second insulation layer formed on the first insulation layer. A top surface of the fuses and an interface between the first insulation layer and the second insulation layer are generally at an identical level.
Certain embodiments also relate to a semiconductor device including a plurality of fuses spaced apart from one another, the fuses including an upper layer thereon. The device also includes a first insulation layer located between adjacent fuses, and a second insulation layer formed on the first insulation layer. A top surface of the upper layer on the fuses and an interface between the first insulation layer and the second insulation layer are at an identical level.
Certain embodiments also relate to a semiconductor device including a plurality of fuses, wherein the fuses are adapted to be fused by irradiation of a laser beam. The device also includes a first insulation layer disposed between adjacent ones of the fuses, a second insulation layer formed on the first insulation layer, and a dielectric layer disposed under the fuses. An interface between the first insulation layer and the second insulation layer is positioned so that when at least one of the fuses is being fused by irradiation of the laser beam, cracks are formed at a level above that of the at least one of the fuses prior to any cracks being formed in the dielectric layer below the at least one of the fuses.


REFERENCES:
patent: 6320243 (2001-11-01), Jeong et al.
patent: 8366503 (2002-04-01), Sonada
patent: 6413848 (2002-07-01), Giust et al.
patent: 6433406 (2002-08-01), Kagiwata
patent: 6509624 (2003-01-01), Radens et al.
patent: 2002/0125576 (2002-09-01), Koyama et al.
patent: 2003/0038304 (2003-02-01), Mori
patent: 2003/0038339 (2003-02-01), Mori
patent: 09-172087 (1997-06-01), None
patent: 11-087521 (1999-03-01), None
patent: 11-260922 (1999-09-01), None
patent: 2000-243845 (2000-09-01), None
patent: 2000-268699 (2000-09-01), None
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-224669 (from which priority is claimed for 10/202,044) dated Jun. 10, 2003 (which lists 09-172087 cited above).
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-224690 (from which priority is claimed for 10/202,063) dated Jun. 10, 2003(which lists 11-260922 and 2000-243845 cited above).
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-224688 (from which priority is claimed for 10/202,028) dated Jun. 10, 2003 (which lists 2000-268699 and 11-087521 cited above).

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