Static information storage and retrieval – Hardware for storage elements
Reexamination Certificate
2001-04-30
2002-08-27
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Hardware for storage elements
C365S063000
Reexamination Certificate
active
06442056
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to packaged semiconductor chip devices which have mirrored external terminals. The present invention further relates to memory modules and other devices which include such mirrored packaged semiconductor chip devices, test devices for testing mirrored packaged semiconductor devices, and methods of testing such mirrored packaged semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor chip devices, or so-called “dice,” are well known in the art. Such devices may include combinations of any of a large number of active semiconductor components, such as diodes and/or transistors, with various passive components, such as capacitors and/or resistors, all residing on a wafer, e.g., made of silicon or gallium arsenide, or other materials. Many different types of semiconductor chip devices are made using different combinations of materials and known manufacturing procedures. Typically, a starting substrate, such as a thin wafer of silicon, is subjected to various combinations of steps such as material deposition, oxidizing, nitridizing, ion implantation, diffusion, doping, masking, etching and others. In these treatments, the specific materials and sequence of steps are selected so as to produce semiconductor components having specific desired functions. The semiconductor components are arranged so as to provide a semiconductor chip device having specified functions, for example, as a memory, such as an SRAM or a DRAM, as is well known in the art.
Each semiconductor chip device has a plurality of die bond pads positioned on or in the chip device which are connected to external terminals or “pins” of an integrated circuit package. It is through these terminals or pins of a package that the semiconductor chip device, and thus the semiconductor components in the chip, electrically communicate with the outside world.
Each different terminal or pin connects to circuitry in or on the semiconductor chip device which provides a particular function. For example, a memory chip may have input-output lines (such as data lines), input only lines (such as clock lines or address lines), ground lines, and one or more power lines. It is through these individual connections that the semiconductor chip device derives all necessary power, ground, input-output and input only signals. There are a variety of known semiconductor chip devices and associated packages which include a large number of such terminals, and as chips become even more dense and feature rich, the number of external terminals required continues to grow.
A common example of a commercial article which includes packaged memory chip devices is a memory module. A memory module typically includes several packaged memory chip devices mounted on a module board, e.g., a printed circuit board. In such a module, each packaged memory chip device has a plurality of external terminals electrically connected to a respective module board electrical connector. The module board provides physical support for the packaged semiconductor device, and electrically connects it to other external circuitry via the module board electrical connectors.
Examples include single in-line memory modules (SIMM's), which are multi-chip memory modules having multiples of the same basic die. In a SIMM, the semiconductor memory chips are typically aligned in a row and interconnected on a printed circuit board to, in effect, create a single device with the memory capacity of the combined memory chips. The wiring pattern of the printed circuit board connects packaged semiconductor devices to module terminals, e.g., along one edge of the printed circuit board. The module terminals may be configured for attachment to an edge-type connector, such as a SIMM socket, as is known in the art.
Another known memory module is a dual in-line memory module (DIMM). On a DIMM, memory chips are mounted on both surfaces of a circuit board. To simplify the mounting and wiring of a memory module having packaged memory chips on both sides of the module board, mirrored packaged memory chips have been developed, so that a packaged memory chip can be mounted on one side of the board and a mirror image of the packaged memory chip can be mounted to the same module board pads on the other side of the board. Such pairs of packaged memory chips are referred to as “mirror pairs” or “mirror images”, i.e., the external terminals of each mirror pair are positioned opposite one another on opposite surfaces of the module and connect to the same board bonding site. The expressions “mirror pair” and “mirror image” are used herein to refer to pairs of packaged memory chips having external terminal arrangements which are asymmetrical. The external terminal arrangements of members of a mirror pair, e.g., memory chips, which are mirror images of each other, are necessarily non-identical. The expression “mirror pair” is used herein to refer to the packaged memory chips whether or not one or both of them are attached to a module board (i.e., on opposite sides of the module board). Also, one member of a mirror pair is referred to herein as a “mirror pair” of the other member and/or a “mirror image” of the other member.
In the manufacture of any of the many articles which include one or more packaged semiconductor chip devices, e.g., memory devices, it has been found that it is inefficient and wasteful to construct the entire article, or a substantial part of it, and later discover that one or more of the packaged semiconductor chip devices is defective or damaged. Therefore, packaged semiconductor chip devices are usually tested prior to mounting them on a circuit board or module. For example, such testing includes testing the die devices for speed and for errors which may occur after fabrication and after burn-in. Burn-in testing is typically conducted at elevated potentials and for a prolonged period of time (e.g., 24 hours), at varying and reduced and elevated surrounding temperatures (such as −15° C. to 125° C.). Such burn-in testing is designed to accelerate failure mechanisms such that die devices which have the potential to prematurely fail during normal operation can be identified and eliminated.
Test devices typically include electrical contact elements (or test head pads), as well as structure, such as a socket or other connection, which acts alone or in combination with a carrier to hold the article being tested at a specific location and in a specific orientation. Since the article is constructed so as to conform to specific dimensional specifications, the electrical contact elements in the test devices reliably make electrical connection with the respective die bondpads on the article, or they make connection with respective elements, e.g., external package terminals, which are in electrical connection with the internal semiconductor device circuitry.
The testing of the packaged semiconductor chip device typically comprises a first series of electrical tests, burn-in of the chip, and a second series of electrical tests. The electrical tests may comprise, for instance, a set of tests to verify that the semiconductor die meets certain speed specifications, a set of tests to verify that the chip device meets specific voltage, capacitance and current specifications, and a set of tests to verify that the chip properly performs the function or functions for which it was designed and over a desired lifespan.
Test devices, including a burn-in oven and test equipment, are relatively expensive. In addition, test devices require electrical circuitry which is specific to the external terminal arrangement on the packaged device being tested. For example, with the test device described above, for each type of packaged device (i.e., for each external terminal arrangement), it is necessary to have a specially designed lid and/or a specially designed carrier.
In the case of mirrored packaged memory chips, the two members of a mirror pair have different (i.e., mirror image) external terminal arrangements, which are not identical to one another. It has
Hamren Steven L.
Nuxoll James P.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Ho Hoai V.
Le Thong
Micro)n Technology, Inc.
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