Semiconductor devices having compensated buffer layers

Details Semiconductor devices having compensated buffer layers Semiconductor devices having compensated buffer layers

1985-12-24

1988-05-17

Carroll, James

357 61, 357 63, 357 64, 357 89, 357 90, H01L 2980, H01L 29167, H01L 29207, H01L 29227

Patent

active

047454482

ABSTRACT:
A field effect transistor includes a substrate of gallium arsenide having a resistivity of at least about 10.sup.7 ohm/cm and a first buffer layer of gallium arsenide disposed over the substrate having a deep level acceptor dopant incorporated into the buffer layer to compensate for donor dopants incorporated into the buffer layer. The concentration of the donor dopants and the acceptor dopant are controlled to provide the buffer layer with a predetermined resistivity characteristic of about 10.sup.7 -10.sup.8 ohm/cm. The concentration of the deep acceptor dopant is substantially constant at about 10.sup.16 acceptors/cc throughout the first buffer layer. The buffer layer preferably has a thickness of at least 2 microns and preferably between 5 and 30 microns. A second buffer layer is disposed over the first buffer layer having a monotonically declining concentration of chromium dopant from about 10.sup.16 to less than about 10.sup.14 acceptors/cc. An active layer and contact layer of suitably n-type doped gallium arsenide are consecutively disposed over at least portions of the second buffer layer.

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patent: 4279670 (1981-07-01), Steele
patent: 4593301 (1986-06-01), Inata et al.
patent: 4688062 (1987-08-01), Liles

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