Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device
Reexamination Certificate
2002-02-05
2004-04-20
Loke, Steve (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
C257S334000, C257S206000, C257S342000, C257S339000, C257S374000, C257S487000, C257S488000, C257S489000
Reexamination Certificate
active
06724021
ABSTRACT:
This invention relates to semiconductor devices with trenched field-shaping regions extending through a voltage-sustaining zone. The invention provides such devices with an advantageous peripheral termination.
Many known types of semiconductor device comprise a semiconductor body that includes a voltage-sustaining zone between first and second device regions that have respective electrode connections adjacent to respective first and second opposite surfaces of the body. Field-effect transistors, for example MOSFETs, are one specific type having the voltage-sustaining zone as a drain drift region of the transistor. Power rectifiers, for example Schottky diodes or p-n junction diodes, are another specific type, in which the voltage-sustaining zone adjoins the rectifying junction.
Published German patent application DE-A-198 48 828 and the PCT published international patent applications WO 01/59844, WO 01/59847 and WO 01/59846 (our refs. PHNL000065; PHNL000066; PHNL000067) disclose the incorporation into such devices of trenched field-shaping regions including a resistive path that extends in trenches through the voltage-sustaining zone to the second electrode region; the trenches extend into the body from the first surface. The voltage-sustaining zone is so dimensioned and doped between the trenched field-shaping regions as to be depleted of free charge carriers between the trenched field-shaping regions in a voltage-blocking mode of operation.
This incorporation of trenched field-shaping regions enables desired voltage-sustaining, voltage-blocking, breakdown voltage characteristics of the devices to be obtained using a semiconductor region (or interposed semiconductor regions) that has (or have) a higher dopant concentration, and thus lower resistivity, than would conventionally be required by a conventional square law relationship between breakdown voltage and series resistivity. These devices are a modification of those disclosed in U.S. Pat. No. 4,754,310 (our reference PHB32740). The whole contents of U.S. Pat. No. 4,754,310, DE-A-198 48 828, WO 01/59844, WO 01/59846 and WO 01/59847 are hereby incorporated herein as reference material.
The various design parameters of the trenched field-shaping regions and voltage-sustaining zone can be optimised to generate a substantially uniform electric field distribution in the active device area between the first and second electrodes, as a result of the passage of a small leakage current through the trenched field-shaping regions. However, such devices are susceptible to deviations in the field profile that might occur near the periphery of the active area.
It is an aim of the present invention to provide a compatible but different scheme of trenched field-shaping regions in the peripheral area so as to reduce device susceptibility to deviations in the field profile in this area.
According to one aspect of the present invention, there is provided a semiconductor device in which the voltage-sustaining zone and the trenched field-shaping regions are present in both an active device area between the first and second electrode-connected regions and in a peripheral area that extends around the periphery of the active area. In the peripheral area, there is included a further resistive path that extends across the first surface, outwardly over the peripheral area. This further resistive path provides a potential divider that is connected to the underlying second region via respective resistive paths of the successive trenched field-shaping regions in the peripheral area. Thereby a gradual variation is achieved in the potential applied by the successive trenched field-shaping regions in the peripheral area of the voltage-sustaining zone.
The use of a resistive path to provide a potential divider over the peripheral area of a semiconductor device is known from U.S. Pat. No. 4,375,125 (our ref. PHB32700), the whole contents of which are hereby incorporated herein as reference material. However, this known use is not in the context of connections to trenched field-shaping regions that themselves include a resistive path to an underlying device region.
In a device in accordance with the present invention, the resistance of the further resistive path that provides the potential divider is typically an order of magnitude lower than the resistance of the resistive path of the trenched field-shaping regions. Although a linear potential gradient may be used along the potential divider, a more compact structure can be achieved by increasing the resistance of the further resistive path to a higher value towards outermost trenched field-shaping regions. This is achievable because the device sensitivity to a lateral field around the outermost regions is diminished after the inner field-shaping regions have gradually dropped a large fraction of the applied voltage.
REFERENCES:
patent: 4375125 (1983-03-01), Byatt
patent: 4754310 (1988-06-01), Coe
patent: 6452230 (2002-09-01), Boden
patent: 19848828 (2000-05-01), None
patent: WO0159844 (2001-08-01), None
patent: WO0159846 (2001-08-01), None
patent: WO0159847 (2001-08-01), None
Hurkx Godefridus A. M.
Rochefort Christelle
Van Dalen Rob
Koninklijke Philips Electronics , N.V.
Loke Steve
Magee Thomas
Waxler Aaron
LandOfFree
Semiconductor devices and their peripheral termination does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor devices and their peripheral termination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor devices and their peripheral termination will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3230904