Semiconductor devices and methods for manufacturing the same

Details Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods for manufacturing the same

2002-10-15

2004-03-23

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S510000, C257S511000, C257S514000

Reexamination Certificate

active

06710421

ABSTRACT:

Applicant hereby incorporates by reference Japanese Application No. 2001-316822, filed Oct. 15, 2001, in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for manufacturing the same, and includes semiconductor devices characterized by their contact layer and methods for manufacturing the same.
RELATED ART
As a technology for forming a contact layer that mutually connects wirings in different layers, for example, the following technology is known.
The technology is described with reference to
FIG. 9. A
first interlayer dielectric layer
212
is formed on a semiconductor substrate
210
where elements such as semiconductor elements are formed. A first conductive layer is formed on the first interlayer dielectric layer
212
, and the first conductive layer is patterned by lithography technique and dry etching to form a lower wiring layer
220
. A second interlayer dielectric layer
230
is formed on the lower wiring layer
220
and the first interlayer dielectric layer
212
.
Then, a resist layer having a specified pattern is formed on the second interlayer dielectric layer
230
. The resist layer has an opening section above a region where a through hole is to be formed. Using the resist layer as a mask, the second interlayer dielectric layer
230
is dry etched to form a through hole
240
that reaches the lower wiring layer
220
.
Next, a conductive material is filled in the through hole
240
, to form a contact layer
250
. A second conductive layer is formed over the second interlayer dielectric layer
230
and the contact layer
250
, and the second conductive layer is patterned by lithography technique and dry etching to form an upper wiring layer
260
.
In the aforementioned technology, in order to lower and stabilize the contact resistance, some measures are taken before forming the contact layer to recover damages caused by the etching step conducted at the time of forming the through hole, to remove contamination with impurities such as heavy metal, carbon, oxygen and fluorine, to remove products of the etching, and the like. Methods to remove damaged layers caused by the etching and impurity contamination include a method in which the interior surface of the through hole is slightly oxidized to include these damage layers, and the oxides are etched; a method in which only the surface layer is slightly etched by a dry etching method using reactive gases; a method in which they are physically removed by a sputter etching method with gases such as argon gas.
SUMMARY
Certain embodiments relate to a semiconductor device including a first wiring layer and an interlayer dielectric layer formed above the first wiring layer. The device also includes a second wiring layer formed above the interlayer dielectric layer, and a through hole formed in the second wiring layer and the interlayer dielectric layer. A contact layer is formed in the through hole and electrically connects the first wiring layer and the second wiring layer.
Certain embodiments also relate to a method for manufacturing a semiconductor device, including: (a) forming a first wiring layer; (b) forming an interlayer dielectric layer above the first wiring layer; (c) forming a conductive layer above the interlayer dielectric layer; (d) forming a through hole in the conductive layer and the interlayer dielectric layer, wherein the through hole reaches the first wiring layer; (e) forming a contact layer in the through hole; and (f) patterning the conductive layer to form a second wiring layer.
Certain embodiments also relate to a semiconductor device including a first electrically conducting layer, an interlayer dielectric layer formed on the first electrically conducting layer, and a second electrically conducting layer formed on the interlayer dielectric layer. The device also includes a through hole extending through the second electrically conducting layer and the interlayer dielectric layer, and a third electrically conducting layer that is disposed in the through hole.


REFERENCES:
patent: 6548338 (2003-04-01), Bernstein et al.
patent: 2002/0046880 (2002-04-01), Takubo et al.

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