Semiconductor devices and methods for manufacturing the same

Details Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods for manufacturing the same

2001-05-01

2003-06-17

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Low workfunction layer for electron emission

C127S010000, C127S070000, C127S070000

Reexamination Certificate

active

06580088

ABSTRACT:

Applicants hereby incorporate by reference Japanese Application No. 2000-132338, filed May 1, 2000 in its entirety. Applicants hereby incorporate by reference U.S. application Ser. No. 09/847,163 in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for manufacturing the same, including semiconductor devices having an improved dielectric strength and methods for manufacturing the same.
RELATED ART
Presently, there is known a field effect transistor having a LOCOS (Local Oxidation Of Silicon) offset structure, which is a field effect transistor having an improved dielectric strength. A field effect transistor having a LOCOS offset structure is a transistor in which a LOCOS layer is provided between a gate dielectric layer and a drain region, wherein an offset impurity layer is formed below the LOCOS layer. For example, Japanese patent No. 2705106 and Japanese patent No. 2534508 describe field effect transistors having a LOCOS offset structure.
It is noted that a field effect transistor having a LOCOS offset structure has a problem in which a bird's beak is formed at an end of the LOCOS such that the active region is narrowed.
SUMMARY
One embodiment relates to a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a source region and a drain region, wherein a semi-recessed LOCOS layer is provided between the gate dielectric layer and the drain region. In addition, an offset impurity layer is provided below the semi-recessed LOCOS layer.
Another embodiment relates to a method for manufacturing a semiconductor device having a field effect transistor, the field effect transistor including a gate dielectric layer, a source region and a drain region, wherein a semi-recessed LOCOS layer is provided between the gate dielectric layer and the drain region, and an offset impurity layer is provided below the semi-recessed LOCOS layer. The method includes forming a recessed section in a region where the semi-recessed LOCOS layer is to be formed, and implanting an impurity in a semiconductor substrate in the recessed section. The method also includes thermally oxidizing the semiconductor substrate to form the semi-recessed LOCOS layer in the recessed section.
Another embodiment relates to a semiconductor device including first and second field effect transistors that each include a gate dielectric layer and source and drain regions. The first and second field effect transistors also each include a semi-recessed LOCOS layer positioned between the gate dielectric layer and the drain region, and an offset impurity layer below the semi-recessed LOCOS layer. The semiconductor device also includes an element isolation region located between the first and second field effect transistors.


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patent: 2534508 (1989-02-01), None
patent: 2705106 (1989-11-01), None

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