Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2000-06-22
2002-07-09
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S099000
Reexamination Certificate
active
06417718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device which can always operate normally upon mounting on the printed circuit board after packaging, regardless of the orientation in which the device is inserted onto a circuit board.
2. Description of the Background Art
FIG. 22
is a schematic illustrating a structure of a conventional semiconductor device. Referring to
FIG. 22
, semiconductor device
1
is rectangular in shape, and has pin terminals
2
A-
0
to
2
A-n arranged along one longer side for electric connection to an external device and pin terminals
2
B-
0
to
2
B-n arranged along the other longer side for electric connection to an external device. Power supply voltage VCC is applied to pin terminal
2
A-
0
and ground voltage VSS is applied to pin terminal
2
B-
0
which is point-symmetrical to pin terminal
2
A-
0
.
Pin terminals
2
A-
1
to
2
A-n receive signals A
1
to An respectively and pin terminals
2
B-
1
to
2
B-n receive signals B
1
to Bn respectively. Although pin terminals
2
A-
1
to
2
A-n and
2
B-
1
to
2
B-n are illustrated as input/output pin terminals for input/output of signals, these pins may be input pin terminals or output pin terminals.
Semiconductor device
1
further includes pads
3
A-
0
to
3
A-n and
3
B-
0
to
3
B-n provided corresponding to respective pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n. Pads
3
A-
0
to
3
A-n and
3
B-
0
to
3
B-n are connected electrically to corresponding pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n via bonding wires, respectively.
Supply voltage VCC applied to pin terminal
2
A-
0
is supplied to a chip internal circuit
6
via pad
3
A-
0
and ground voltage VSS applied to pin terminal
2
B-
0
is supplied to chip internal circuit
6
via pad
3
B-
0
. Chip internal circuit
6
may perform a predetermined processing using supply voltage VCC applied to pin terminal
2
A-
0
as one operating supply voltage, or chip internal circuit
6
may be configured to lower supply voltage VCC applied to pin terminal
2
A-
0
to generate an operating supply voltage.
Buffer circuits
4
A-
1
to
4
A-n are arranged corresponding to pads
3
A-
1
to
3
A-n respectively and buffer circuits
4
B-
1
to
4
B-n are arranged corresponding to pads
3
B-
1
to
3
B-n respectively. Although buffer circuits
4
A-
1
to
4
A-n and
4
B-
1
to
4
B-n are illustrated as input/output buffer circuits, they may be input buffer circuits or output buffer circuits. These buffer circuits
4
A-
1
to
4
A-n and
4
B-
1
to
4
B-n serve as an interface for signals between an external device and chip internal circuit
6
to buffer those signals supplied respectively thereto and transmit the buffered signals to chip internal circuit
6
or the external device.
A package of semiconductor device
1
as shown in
FIG. 22
is usually called DIL (Dual In Line) package having pin terminals arranged along the longer sides of the rectangular package. In this structure, semiconductor device
1
formed on a semiconductor chip is sealed by such a package and electrically connected to an external device via the pin terminals. In this way, fine-processed semiconductor device
1
can be connected electrically to any external device via pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n. Further, when the semiconductor device is inserted to a circuit board, pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n enable the semiconductor device to be mounted on the circuit board easily.
For semiconductor device
1
shown in
FIG. 22
, pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n are arranged in alignment in the direction of the longer sides of the rectangular device, each pin terminal is specified by a pin number, and a predetermined signal/voltage is input/output to/from each pin terminal. Pin terminals
2
A-
0
to
2
A-n and
2
B-
0
to
2
B-n are formed of a leadframe and all are identical in shape. In order to clearly distinguish the top and bottom of semiconductor device
1
, a mark (concave)
20
indicating the top/bottom is formed on one of the shorter sides on a surface of the package of semiconductor device
1
as shown FIG.
23
. Concave
20
indicates the top/bottom of the semiconductor device. Even with semiconductor device
1
upside-down, the pin terminals can be inserted to an IC socket, for example, of a circuit board since the pin terminals have the same pitch.
If semiconductor device
1
is mounted on the circuit board with its top and bottom reversed and power is supplied to the entire circuit board, signals/voltages applied to the pin terminals are not normal ones so that a normal operation of semiconductor device
1
is impossible. In general, in order to prevent short circuit in the DIL package, pin terminal
2
A-
0
receiving supply voltage VCC and pin terminal
2
B-
0
receiving ground voltage VSS are arranged point-symmetrically to each other as shown in FIG.
22
. If semiconductor device
1
having such a pin arrangement is mounted on the circuit board with its top and bottom reversed, or upside down, positions of pin terminals
2
A-
0
and
2
B-
0
are replaced with each other. Consequently, pin terminal
2
B-
0
which should receive ground voltage VSS receives supply voltage VCC and pin terminal
2
A-
0
which should receive supply voltage VCC receives ground voltage VSS. Thus, a ground line which should be fixed at ground voltage VSS is set at supply voltage VCC level in chip internal circuit
6
of semiconductor device
1
, resulting in a large current flow therein which generates heat and resultant damage to internal elements due to the generated heat. Such a large current flows through a path discussed below, for example.
FIG. 24
shows a structure of a signal input portion of semiconductor device
1
. Referring to
FIG. 24
, a pad PD is coupled to a buffer circuit BF by a signal line SG. A diode DF
0
is connected between signal line SG and a supply node PS
0
and a diode DF
1
is connected between signal line SG and a supply node (ground node) PS
1
. Diode DF
0
has its anode connected to signal line SG and its cathode connected to supply node PS
0
. Diode DF
1
has its anode connected to ground node PS
1
and its cathode connected to signal line SG.
When semiconductor device
1
is inserted to a circuit board in a normal orientation, supply node PS
0
and ground node PS
1
receive supply voltage VCC and ground voltage VSS, respectively. A positive surge voltage applied to pad PD is discharged to supply node PS
0
via diode DF
0
. If a negative surge voltage is generated on pad PD, diode DF
1
becomes conductive to cause current to flow from ground node PS
1
to signal line SG and accordingly the negative surge voltage is absorbed.
If semiconductor device
1
is inserted to the circuit board in the opposite orientation, ground voltage VSS is applied to supply node PS
0
and supply voltage VCC is applied to ground node PS
1
. In this case, diodes DF
1
and DF
0
are always in ON state, so that a large current constantly flows through this path.
Further, in the chip internal circuit, an output level of a logic gate circuit and the like is inverted. If this insertion of the device in the opposite orientation causes all logic levels of internal signals to be inverted, or of an output signal of a row decoder and a logic level (voltage level) of a word line drive signal in a semiconductor memory device change, for example, a word line which should be grounded when it is not selected is driven to the supply voltage VCC level, causing a large current in a word line drive portion.
If such semiconductor device
1
is mounted in the reverse orientation on the circuit board, a problem arises that failure occurs in the semiconductor device and accordingly the overall system cannot operate normally.
For adaptation to the insertion to the circuit board of a semiconductor device in the reverse orientation, a structure has been devised in which the internal circuit is set into an in-operable state
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Wells Kenneth B.
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