Semiconductor device with wiring substrate

Details Semiconductor device with wiring substrate Semiconductor device with wiring substrate

2000-11-09

2002-06-04

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000

Reexamination Certificate

active

06400019

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device technique and, more particularly, to a technique effective when applied to a semiconductor device technique having a high-frequency signal processing circuit.
As a small-sized electronic device such as a mobile telephone or a portable computer comes into wide use, it has been promoted to reduce the size and thickness of a semiconductor device constituting the electronic device. The BGA (Ball Grid Array), the LGA (Land Grid Array) or the CSP (Chip Size Package) is a package structure for promoting the reduction in the size and thickness, for which various devices have been made. For example, the CSP is the general naming of the package which is equivalent or slightly larger than the size of the semiconductor chip, and can realize the size thickness reduction and shorten the internal wiring length so that it has been practiced as the package structure for reducing the signal delay or noise.
In the package structure for realizing the size thickness reductions, however, there are problems of: the difficulty in damping the stress because the connections between the semiconductor device and the wiring substrate for mounting the semiconductor device are comprised of bump electrodes and fixed; and a low junction strength because the bump electrodes have small contact areas. These problems have been described on pp. 48 to 55 of “Nikkei Microdevice, February, 1998”, as issued by Kabushiki Gaisha Nikkei BP on Feb. 1, 1998, which has disclosed the optimization of the contact areas and the materials of the bump electrodes.
SUMMARY OF THE INVENTION
In the technique for optimizing the contact area of the bump electrodes so as to improve the junction strength, however, the adjoining spacing between the bump electrodes is widened to enlarge the area (i.e., the contact area) . Therefore, we have found that there arises a problem contrary to the size reduction of the semiconductor device.
On the other hand, we have searched the examples of the prior art from the standpoint of the junction strength of the bump electrodes on the basis of the invention, and have found out Unexamined Published Japanese Patent Applications Nos. 7-22538 and 7-193162. In these Publications, there is disclosed a technique by which larger bump electrodes and smaller bump electrodes are arranged on the back surface of a package substrate, but the larger bump electrodes enlarge the diameter.
In Unexamined Published Japanese Patent Application No. 9-307022, on the other hand, there is disclosed a structure in which the diameter of solder balls in the outer periphery of a solder ball arranging area on the back surface of a package substrate is made larger than that of the remaining solder balls so as to prevent the fatigue failures of the solder balls, as might otherwise be caused by the stress between the package substrate and the printed-circuit board.
In Unexamined Published Japanese Patent Application No. 11-154718, on the other hand, there is disclosed a structure in which the diameter of the solder joint portions near the corners of a semiconductor chip is made larger than that of the remaining solder joint portions so as to prevent the fatigue failures of the solder joint portions, as might otherwise be caused by the stress between the ceramic substrate and the printed board.
An object of the invention is to provide a technique for improving the junction strength between the external terminals and the wiring substrate of a semiconductor device without increasing the top plan size of the semiconductor device.
The aforementioned and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
The representatives of the invention to be disclosed herein will be summarized in the following.
According to the invention, specifically, a plurality of external terminals having different top plan sizes in the longitudinal and transverse directions are arranged in the outer periphery of the back surface of a wiring substrate for mounting a semiconductor chip.
According to the invention, on the other hand, a plurality of external terminals, the top plan size of which is larger in the direction to intersect the sides of a wiring substrate for mounting a semiconductor chip is larger than the top plan size in the direction in parallel with the sides, are arranged in the outermost periphery of the back surface of the wiring substrate.
According to the invention, on the other hand, a plurality of rectangular external terminals having rounded corners are arranged in the outermost periphery of the back surface of a wiring substrate for mounting a semiconductor chip.


REFERENCES:
patent: 5859474 (1999-01-01), Dordi
patent: 7-22538 (1995-01-01), None
patent: 7-193162 (1995-07-01), None
patent: 9-307022 (1997-11-01), None
patent: 11-154718 (1999-06-01), None
“The Next Generation of LSI Packaging Technology,” Nikkei Microdevices, Kabushiki Gaisha Nikkei BP, Feb. 1, 1998, pp. 48-55 (with translation).
“The Next Generation of LSI Packaging Technology,” Nikkei Microdevices, Kabushiki Gaisha Nikkei BP, Feb. 1, 1998, pp. 48-55 (with translation).

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