Semiconductor device with varying dummy via-hole plug density

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S758000, C257S774000, C257SE23011, C257SE23067, C257SE21577

Reexamination Certificate

active

07470981

ABSTRACT:
The present invention is concerned with a method for producing a semiconductor device wherein lower-layer wirings and upper-layer wirings are formed with an interlayer insulating film therebetween, and the lower-layer wirings are electrically connected to the upper-layer wirings via via-hole plugs. Over a semiconductor substrate, the interlayer insulating film is formed to cover the lower-layer wirings. In the interlayer insulating film, via-holes for exposing surfaces of the lower-layer wirings are formed, and simultaneously, in a region of the interlayer insulating film where no via-holes exist, dummy via-holes which are not deep enough to reach down to the lower-layer wirings are formed. The dummy via-holes are formed in such a manner that the density of the dummy via-holes gradually decreases from a region where the via-holes are formed. Over the semiconductor substrate, a metal layer is formed to fill the via-holes and the dummy via-holes. A portion over the semiconductor substrate is polished thereby forming the via-hole plugs and dummy via-hole plugs. The upper-layer wirings are formed in such a manner that the upper-layer wirings come in contact with the via-hole plugs. According to this method, a semiconductor device that has high flatness of the interlayer insulating film is obtained.

REFERENCES:
patent: 6313497 (2001-11-01), Iwasa
patent: 6342734 (2002-01-01), Allman et al.
patent: 6541335 (2003-04-01), Iwasa
patent: 6657247 (2003-12-01), Yoshiyama et al.
patent: 6998663 (2006-02-01), Yoshitomi et al.
patent: 8-222632 (1996-08-01), None
patent: 1999-0075978 (1999-10-01), None
patent: 2000-0019031 (2000-04-01), None

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