Semiconductor device with variable pin locations

Details Semiconductor device with variable pin locations Semiconductor device with variable pin locations

2000-05-24

2002-10-15

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S041000, C257S499000, C257S203000, C257S208000

Reexamination Certificate

active

06465884

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and in particular, to semiconductor devices with variable pin locations.
DESCRIPTION OF THE RELATED ART
Semiconductor devices (e.g., integrated circuits (ICs)) have wide-reaching and varied uses in the technology industry. Predominantly, semiconductor devices are used as the building blocks for computer processing devices. Semiconductor devices provide the logic by which today's computers organize and process information. They are many different types of semiconductor devices on the market, all of differing size and configuration.
One of the differences between semiconductor devices is the number of terminals, or “pins” that each possesses. As is well known, the pins of an semiconductor device provide terminals by which signals may be fed to, or issued from, the device. Some common types of semiconductor devices may include anywhere from 4 to 1000 pins per device.
FIG. 1
shows a conventional 16-pin semiconductor device
10
. The semiconductor device
10
includes a plurality of pins
20
(labeled
1
-
16
) and logic circuitry
30
coupled to the pins in a specific manner. As is known in the art, the pins
20
are assigned certain functions at the time of manufacture of the device. For instance, in the 16-pin semiconductor device shown in
FIG. 1
, pins
1
-
8
may comprise input pins and pins
9
-
16
may comprise output pins. Of course there are various types of inputs and outputs which may be coupled to the device (e.g., clock signals, operation signals, reset signals, etc.), and each must be coupled to the logic circuitry
30
in a particular manner. More specifically, if pin
8
is a “reset” pin, it must be coupled to the portion of the logic circuitry which controls resetting. In
FIG. 1
, that portion of the logic circuitry
30
which controls resetting is presumed to be located on the ‘south’ side of the logic circuitry. However, in some other semiconductor device designs, the resetting circuitry may be disposed on a ‘north’, a ‘west’, or an ‘east’ side of the logic circuitry
30
. Thus, as will be understood, it would be beneficial to create an semiconductor device which allows any one of the pins
1
-
16
to be a “reset” pin.
The physical pin arrangement (e.g., number of pins, pin position) of an semiconductor device is determined at the time the device is manufactured, and will remain fixed regardless of the package types in which the device is enclosed. Thus, a complete and expensive new mask set will be needed each time the pin arrangement is altered.
As stated above, a problem associated with the current techniques for manufacturing semiconductor devices is that each time a new device type (with a different pin arrangement scheme) is produced, the “masks” which are used to produce the device must be changed. Often times, ten (10) or more masks must be used each time a new semiconductor device is manufactured. The changing of masks adds considerably to the time and costs associated with device production.
Therefore, there is currently a need for an semiconductor device design which allows pin assignments to be varied, without the need for changing masks.
SUMMARY OF THE INVENTION
The present invention is an semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry.
The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention which is provided in connection with the accompanying drawings.


REFERENCES:
patent: 5453991 (1995-09-01), Suzuki et al.
patent: 5922055 (1999-07-01), Shahar et al.
patent: 6097988 (2000-08-01), Tobias

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