Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-06-01
2002-06-25
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S124000
Reexamination Certificate
active
06410365
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and a technique for producing a semiconductor device, and in particular to an effective technique for producing a semiconductor device by stacking two semiconductor chips, and sealing them by a single resin body.
With the trend towards larger capacities, semiconductor chips which incorporate storage systems such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) are assuming larger flat sizes. In semiconductor devices wherein a semiconductor chip containing a storage circuit system is sealed by a resin body, a lead frame diepad (known also as a tab) is omitted, and a LOC (Lead on Chip) structure is used which can also be applied to large semiconductor chips. In an LOC structure, leads are disposed on the upper surface (i.e., a main surface) of upper and lower surfaces (a main surface and another main surface opposite to it) of a semiconductor chip. By adopting this LOC structure, a seal region can be retained for leads sealed by a resin body even when the flat size of the semiconductor chip increases, so increased flat size of the resin body is suppressed. A semiconductor device using an LOC structure is disclosed, for example, in Tokkai Hei 2-246125 published on Oct. 1, 1990 (corresponding to U.S. Pat. No. 5,068,712).
To achieve high packaging density of semiconductor chips comprising storage circuit systems, stacked semiconductor devices have been developed wherein two semiconductor chips having storage circuit systems of identical capacity are stacked, and the two chips are then sealed by one resin body. A stacked semiconductor device having an LOC structure is disclosed, for example, in Tokkai Hei 7-58281 (published on Mar. 3, 1995).
The stacked semiconductor device having an LOC structure disclosed in this publication essentially comprises a resin body, first and second semiconductor chips situated inside the resin body and having an electrode formed on a circuit-forming surface which is the upper surface (i.e., a main surface) of upper and lower surfaces (a main surface and another main surface opposite each other), a first lead extending inside and outside the resin body and bonded to the circuit-forming surface of the first semiconductor chip via an insulating film, and a second lead situated inside the resin body, bonded to the circuit-forming surface of the second semiconductor chip via an insulating film, and electrically connected to the electrode of the circuit-forming surface by an electrically conducting wire.
The first semiconductor chip and second semiconductor chip are both stacked so that their circuit-forming surfaces oppose each other leaving a predetermined gap. The first lead and second lead are laminated so that part of each is superimposed, and electrically and mechanically connected by welding with a laser.
The first lead comprises an inner lead part situated inside the resin body which runs across one side of the circuit-forming surface of the first semiconductor chip and extends over the circuit-forming surface of the first semiconductor chip, and an outer lead part bent into a J-shaped lead, which is one type of surface mounted packege.
The inner lead part of this first lead is bent so that the part which is bonded to the circuit-forming surface of the first semiconductor chip via an insulating film, is nearer to the circuit-forming surface of the chip than the part which runs across one side of the first semiconductor chip.
The second lead runs across one side of the circuit-forming surface of the second semiconductor chip and extends over the circuit-forming surface of the second semiconductor chip. This lead is bent so that the part which is bonded to the circuit-forming surface of the second semiconductor chip via an insulating film, is nearer to the circuit-forming surface of the chip than the part which runs across one side of the second semiconductor chip.
After welding with the laser, the other end of the second lead connected to the second semiconductor chip is cut inside the resin body before the transfer mold step, so it is not pulled out from the body. In other words, the outer lead which is pulled out of the body is used as a common outer connecting terminal for two semiconductor chips.
According to the aforesaid resin molded type semiconductor device, two semiconductor chips forming a memory LSI may be resin-sealed into one thin package, so a high-capacity package having effectively twice the storage capacity can be implemented in the same size as a package comprising one semiconductor chip which has been resin-sealed.
SUMMARY OF THE INVENTION
The inventor is developing a new stacked semiconductor device having an LOC structure suitable for thinner assemblies. This stacked semiconductor device has not yet been disclosed, however, it has the following construction as described in U.S. application Ser. No. 09/161,725 (filed on Sep. 29, 1998) submitted earlier by the Applicant.
The device comprises mainly a resin body, a first and second semiconductor chips situated inside the resin body and having an electrode formed on a circuit-forming surface which is the upper surface (i.e., a main surface) of upper and lower surfaces, a first lead extending inside and outside the resin body, bonded to the circuit-forming surface of the first semiconductor chip via an insulating film, and electrically connected to the electrode of the circuit-forming surface by an electrically conducting wire, and a second lead extending inside and outside the resin body, bonded to the circuit-forming surface of the second semiconductor chip via an insulating film, and electrically connected to the electrode of the circuit-forming surface by an electrically conducting wire.
The stacked semiconductor device of this invention may be, for example, a TSOP (Thin Small Outline Package). Two semiconductor chips, i.e., first and second semiconductor chips, which form memory LSI having the same storage capacities (e.g., a 64 Mbyte DRAM), are stacked on each other inside a package (resin body) formed by the transfer mold method, and are sealed with their lower surfaces (i.e., a main surface and another main surface facing away from each other) in contact.
The first lead and second lead are laminated so that part of each is superimposed, and electrically and mechanically connected by welding with a laser.
The first lead and second lead each comprise an inner lead part situated inside the resin body and an outer lead part situated outside the resin body. The inner lead parts of the first and second semiconductor chips comprise a first part which runs across one side of the circuit-forming surface of the semiconductor chip (first semiconductor chip in the case of the first lead and second semiconductor chip in the case of the second lead) and extends over the circuit-forming surface of the semiconductor chip, a second part which is bent from the first part towards the lower surface of the semiconductor chip, and a third part which extends from the second part in the same direction as the first part. The third parts of the first lead and second lead extend inside and outside the resin body, and are stacked on each other in an up/down direction. The outer lead part of the first lead is bent in a gull-wing lead shape, which is a type of surface mounted package. The outer lead part of the second lead is formed in a shorter length than that of the outer lead part of the first lead.
Hence, in the above stacked semiconductor, device, unlike the stacked semiconductor device of the aforesaid disclosure wherein element forming surfaces of two semiconductor chips are disposed opposing each other and an inner lead part is disposed in the gap between the two, the lower surfaces of two semiconductor chips are brought into contact with each other.
Therefore there is no gap between the two semiconductor chips, and the thickness of the resin body can be made thinner by a corresponding amount.
In other words, as there are no first leads or second leads between the first semiconductor chip and
Fujishima Atsushi
Hagiwara Takatoshi
Kawata Youichi
Koizumi Kouji
Nakajima Yasuyuki
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