Semiconductor device with trench isolation structure and...

Details Semiconductor device with trench isolation structure and... Semiconductor device with trench isolation structure and...

1999-04-28

2001-03-06

Saadat, Mahshid (Department: 2815)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C438S424000, C438S218000, C438S221000, C438S294000, C438S296000

Reexamination Certificate

active

06197661

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with the trench isolation structure and a fabrication method thereof.
2. Description of the Prior Art
The isolation structure is essential for Integrated Circuits (ICs) to electrically isolate electronic elements or devices on a semiconductor substrate. To implement the isolation structure, conventionally, two isolation techniques have been used.
In a first one of the isolation techniques, the isolation dielectric is formed on a main surface of the semiconductor substrate by the well-known LOcal Oxidation of Silicon (LOCOS) method. The isolation dielectric is typically made of a thick silicon dioxide (SiO
2
) layer having a pattern of a wanted isolation region.
In a second one of the isolation techniques, the isolation dielectric is formed to fill a trench formed in a surface region of the semiconductor substrate. The trench has a pattern of a wanted isolation region and is filled with the isolation dielectric, thereby constituting the trench isolation structure. The isolation dielectric is typically made of SiO
2
.
A conventional semiconductor device including the trench isolation structure is shown in FIG.
1
.
In
FIG. 1
, an isolation trench
102
is formed in a surface region of a single-crystal silicon substrate
101
. The trench
102
is filled with an isolation dielectric
103
. As the isolation dielectric
103
, SiO
2
is usually used.
A diffusion region
111
, which is opposite in conductivity type to the substrate
101
, is formed in the surface region of the substrate
101
. The end of the diffusion region
111
is contacted with the opposing edge of the isolation dielectric
103
.
An interlayer insulating layer
110
is formed on the surface region of the substrate
101
to cover the diffusion region
111
and the isolation dielectric
103
. The interlayer insulating layer
110
has a contact hole
114
′ uncovering the diffusion region
111
.
A metallic wiring layer
109
is formed on the interlayer insulating layer
110
to overlap with the diffusion region
111
and the isolation trench
102
. The wiring layer
109
is contacted with and electrically connected to the underlying diffusion region
111
through the contact hole
114
′ of the interlayer insulating layer
110
.
The position of the contact hole
114
′ is designed so that the contact hole
114
′ uncovers the diffusion region
111
alone, in other words, the contact hole
114
′ is not contacted with the isolation dielectric
103
. The designed, correct position of the contact hole
114
′ is indicated by a reference numeral
114
in FIG.
1
.
When the position of the contact hole
114
′ deviates from its correct position
114
due to the positional and/or dimensional fluctuation in the fabrication process sequence, the wiring layer
109
on the interlayer insulating layer
110
tends to be contacted with the substrate
101
at a contact area
112
through the contact hole
114
′ of the interlayer insulating layer
110
and an opening
115
of the isolation dielectric
103
, as shown in FIG.
1
. This is caused by the fact that the isolation trench
102
and therefore the isolation dielectric
103
has vertical walls, which is unlike the isolation structure using the LOCOS method.
Thus, there is a problem that a leakage current flows between the wiring layer
109
and the substrate
101
due to the positional error of the contact hole
114
′.
FIG. 2
shows another cause of the leakage current between the wiring layer
109
and the substrate
101
. For simplification of description, the same reference numerals as those in
FIG. 1
are attached to the same elements in
FIG. 2
, and the interlayer dielectric layer
110
and the metallic wiring layer
109
are omitted.
In
FIG. 2
, the isolation dielectric
103
filling the isolation trench
102
is made of a material with a large stress such as silicon nitride (Si
3
N
4
). Crystal defect regions
113
tend to be generated at the interface of the isolation dielectric
103
with the substrate
101
and the diffusion region
111
after heat treatment. The crystal defect regions
113
will cause the above-described leakage current problem between the diffusion region
111
and the substrate
101
.
The other, relating conventional trench isolation structures are disclosed in the Japanese Non-Examined Patent Publication Nos. 4-27141 published in 1992 and 5-299497 published in 1993.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device with the trench isolation structure in which the above-described leakage current problem does not occur.
Another object of the present invention is to provide a fabrication method of a semiconductor device with the trench isolation structure in which the above-described leakage current problem does not occur.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor device is provided, which is comprised of a semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench.
The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by an etching process.
The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer.
The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator.
The first isolation dielectric has a pair of depressions. Each depression has one side contiguous with one of a pair of top corners of the isolation trench. The pair of depressions of the first isolation dielectric are filled with the second isolation dielectric.
The second dielectric has a lower etch rate in the etching process for forming the contact hole than that of the interlayer dielectric layer.
With the semiconductor device according to the first aspect of the present invention, the isolation trench formed in the surface region of the substrate is filled with the first and second isolation dielectrics, where the first isolation dielectric serves as a primary insulator, and the second isolation dielectric serves as a secondary insulator.
Also, the pair of depressions of the first isolation dielectric, each having one side contiguous with one of the pair of top corners of the isolation trench, are filled with the second isolation dielectric.
Therefore, when the position of the contact hole of the interlayer dielectric layer deviates from its correct position and the contact hole is overlapped with the isolation trench, the etching action is applied to the second dielectric in the isolation trench during the etching process for forming the contact hole of the interlayer dielectric layer.
Because the second dielectric has a lower etch rate in the etching process for forming the contact hole of the interlayer dielectric layer than that of the interlayer dielectric layer, the second dielectric is difficult to be etched.
Thus, the above-described leakage current problem due to etching is prevented from occurring.
Additionally, the isolation trench is filled with the first isolation dielectric serving as a primary insulator and the second isolation dielectric serving as a secondary insulator. Therefore, if a dielectric (e.g., SiN
x
) having a large stress is used as the second isolation dielectric and at the same time, a dielectric (e.g., SiO
2
) having a low stress is used as the first isolation dielectric, no crystal defect is generated at the

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