Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-05-22
2004-06-15
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S520000, C257SE29019, C438S361000, C438S430000
Reexamination Certificate
active
06750526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a manufacturing method for the same, in particular, to a semiconductor device having a trench for isolation and to a manufacturing method for the same.
2. Description of the Background Art
A variety of isolation structures for electrically insolating elements from each other are utilized at the time when a plurality of predetermined elements, such as bipolar transistors, registers or capacitors, are mounted in a semiconductor integrated circuit (hereinafter referred to as IC). The isolation structure that is most widely utilized is an isolation structure based on a PN junction.
In this isolation structure a PN junction is formed between a region wherein elements are formed (element formation region) and an isolation region of which the conductive type is opposite to that of the element formation region. Then, adjoining element formation regions are electrically isolated from each other by applying a reverse bias to this PN junction.
In a bipolar IC, an N
−
type epitaxial layer is allowed to grow on a P
−
type semiconductor substrate. In this case, it is necessary to defuse a P type diffusion layer in the depth direction by the film thickness of the N
−
type epitaxial layer in order to form an isolation region. At this time, the P type diffusion layer spreads in the lateral direction to approximately the same degree as the film thickness of the N
−
type epitaxial layer.
Therefore, an extra distance between an element formation region and an isolation region must be secured by taking the amount of spread in the lateral direction of the above diffusion layer into consideration. In particular, since it is necessary to make the N
−
type epitaxial layer thick in a transistor of a high withstand voltage, the isolation region further spreads in the lateral direction so that the area of the semiconductor device that includes the element formation region and the isolation region becomes great.
In order to overcome this defect, a trench isolation structure has been implemented in recent years. In a trench isolation structure a deep trench is created to reach to a predetermined depth in the P
−
type semiconductor substrate by penetrating the N
−
type epitaxial layer and an insulator is filled in into this trench. Accordingly, a trench isolation structure does not have spread in the lateral direction, unlike in the case of an isolation structure based on a PN junction, and a trench isolation region is formed so as to approximately attain predetermined dimensions so that the density of integration of a semiconductor device can be greatly increased.
In the following, a manufacturing method for a bipolar IC of a trench isolation structure that has an NPN type bipolar transistor is described as a conventional manufacturing method for a semiconductor device.
First, as shown in
FIG. 60
, an N
+
type buried layer
102
is formed on a P type silicon substrate
101
. Next, an N
−
type epitaxial layer is formed in accordance with an epitaxial growth method. Trenches
106
a
and
106
b
are created by carrying out predetermined photomechanical, and other, processes so as to penetrate the N
−
type epitaxial layer and so as to reach to a predetermined depth in P type silicon substrate
101
. Thereby, N
−
type epitaxial layer
103
is divided into three regions, N
−
type epitaxial layers
103
a
to
103
c.
Next, reaction products produced during etching at the time of the creation of trenches
106
a
and
106
b
are removed by carrying out predetermined wet etching or cleaning processes. After that, a thermal oxide film (not shown), which becomes a sacrificial oxide film, is formed on the surface of trenches
106
a
and
106
b.
Next, boron is implanted through this thermal oxide film at an acceleration voltage of 50 KeV with the dosage amount of 1×10
14
/cm
2
and, thereby, channel cut layers
108
a
and
108
b
are formed in regions of P
−
type silicon substrate
101
located at the bottom of trenches
106
a
and
106
b
. After that, the thermal oxide film is removed through wet etching and a thermal oxide film
109
is formed.
Next, as shown in
FIG. 61
, a polysilicon film
110
is formed on thermal oxide film
109
so as to fill in trenches
106
a
and
106
b
. Next, as shown in
FIG. 62
, buried polysilicon films
110
a
and
110
b
are formed by carrying out etching on the entire surface of polysilicon film
110
so as to leave polysilicon film
110
only within trenches
106
a
and
106
b.
Next, as shown in
FIG. 63
, thermal oxide film
109
is allowed to remain only within trenches
106
a
and
106
b
by carrying out wet etching so as to remove thermal oxide film
109
located on N
−
type epitaxial layers
103
a
to
103
c
. At this time, etching is also carried out on portions of thermal oxide film
109
located on the sidewalls in the vicinity of the edges of the openings of trenches
106
a
and
106
b
so that recesses
111
a
to
111
d
are created along the sidewalls in the vicinity of the edges of the openings of trenches
106
a
and
106
b.
Next, as shown in
FIG. 64
, a thermal oxide film
112
is formed on N
−
type epitaxial layers
103
a
to
103
c
by applying a thermal oxidation process. Through this thermal oxidation process, the exposed surface of buried polysilicon films
110
a
and
110
b
is also oxidized.
Accordingly, the surface of buried polysilicon films
110
a
and
110
b
and N
−
type epitaxial layers
103
a
to
103
c
, which are exposed in recesses
111
a
to
111
d
, is also oxidized in the upper portions of trenches
106
a
and
106
b
so that thick oxide films
109
a
and
109
b
are formed between buried polysilicon films
110
a
,
110
b
and N
−
type epitaxial layers
103
a
to
103
c
. Then, recesses
113
a
to
113
d
are created through the formation of thick oxide films
109
a
and
109
b
in thermal oxide film
112
.
Next, as shown in
FIG. 65
, a collector lead-out layer
114
and a base lead-out layer
116
are, respectively, formed by means of a predetermined gas diffusion method. After that, thermal oxide film
112
is removed and a new thermal oxide film
118
is formed. At this time, in the case that etching of thermal oxide film
112
is carried out to an excessive degree, recesses
113
a
to
113
d
are spread so that thicker thermal oxide film is formed on the portions of these recesses
113
a
to
113
d
during thermal oxidation at the time of the formation of thermal oxide film
118
.
Next, as shown in
FIG. 66
, a base diffusion layer
121
is formed by implanting boron ions, for example, into N
−
type epitaxial layer
103
b
by means of an ion implantation method. At this time, a thermal oxidation process is also carried out when boron is diffused by means of a thermal treatment (boron drive) and, thereby, the film thickness of thermal oxide film
118
becomes greater.
Next, as shown in
FIG. 67
, an emitter diffusion layer
124
a
and a collector diffusion layer
124
b
are formed on N
−
type epitaxial layer
103
b
. After that, metal silicide layers
127
a
to
127
c
, such as of TiSi
2
, barrier metal layers
128
a
to
128
c
, such as of TiN, and metal wires
129
a
to
129
c
, such as of AlCu, are, for example, formed. Thereby, an NPN transistor T is completed.
In the above-described conventional manufacturing method for a semiconductor device, however, it is found that the following problems exist. That is to say, when predetermined voltages are applied, respectively, between N
−
type epitaxial layer
103
a
and N
−
type epitaxial layer
103
b
or between epitaxial layer
103
b
and N
−
type epitaxial layer
103
c
, it is found that a comparatively large amount of leak current occurs with the result that the elements formed in the respective N
−
type epitaxial layers
103
a
to
103
c
can not be sufficiently electrically isolated from each other.
SUMMARY OF
Lebentritt Michael S.
McDermott & Will & Emery
Renesas Technology Corp.
Wilson Christian D.
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