Semiconductor device with trench gate

Details Semiconductor device with trench gate Semiconductor device with trench gate

2003-01-16

2004-06-08

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S133000, C257S330000

Reexamination Certificate

active

06747295

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with a trench gate, such as an insulated-gate-type transistor (IGBT (Insulated Gate Bipolar Transistor)).
In an insulated-gate-type semiconductor device such as an IGBT, the conduction loss can be reduced by a buried trench gate. This is because forming a fine trench gate increases the channel density, and forming a deep trench gate promotes conductivity modulation.
FIGS. 20A and 20B
are sectional and plan views, respectively, showing a conventional IGBT with a trench gate.
FIG. 20A
shows a section taken along a line XXA—XXA in FIG.
20
B.
In this IGBT, a p-base layer
102
is formed on an n-base layer
101
. A plurality of trenches
103
having a stripe structure are formed to extend through the p-base layer
102
and reach the n-base layer
101
. In each trench
103
, a gate electrode
104
is buried via a gate insulating film
111
formed on the sidewall and bottom surface. An n-emitter layer
105
is formed in the p-base layer
102
to come into contact with the trench
103
.
An insulating film
108
is selectively formed on the p-base layer
102
, n-emitter layers
105
, and trenches
103
. An emitter electrode
109
is formed on the insulating film
108
and comes into contact with the n-emitter layer
105
and p-base layer
102
through contact holes. A p-emitter layer
107
is formed on the opposite-side surface of the n-base layer
101
via an n-buffer layer
106
. A collector electrode
110
is further formed in contact with the p-emitter layer
107
.
To operate this IGBT, a positive bias is applied across the collector electrode
110
and emitter electrode
109
, and in this state, a positive bias is applied to the gate electrode
104
. At this time, an inversion layer is formed in the p-base layer
102
along the surface of the gate insulating film
111
, and electrons are injected from the n-emitter layer
105
into the n-base layer
101
. On the other hand, holes are injected from the p-emitter layer
107
into the n-base layer
101
in correspondence with the injected electron amount. As the n-base layer
101
is filled with carriers, conductivity modulation occurs. For this reason, the resistance of the n-base layer
101
decreases to turn on the device.
In the IGBT shown in
FIGS. 20A and 20B
, one factor that determines the conduction loss in the ON state is the resistance of the n-base layer
101
when conductivity modulation has occurred. The resistance of the n-base layer
101
depends on the total amount of carriers that fill this layer. The total amount of carriers is determined by the ratio of an electron current to a hole current, flowing from the n-base layer
101
to the p-base layer
102
. As the distance between the trenches
103
, which determines the width of a current path region
131
connected to the emitter electrode
109
, decreases, the resistance in flow of the holes to the emitter electrode
109
through the p-base layer
102
increases. For this reason, the amount of carriers filling the n-base layer
101
increases, and the conduction loss decreases.
However, when the distance between the trenches
103
decreases, the alignment margin between a trench formation mask and a contact formation mask decreases, and the number of defects increases in the manufacturing process, resulting in low yield. To ensure the minimum necessary mask alignment margin, the distance between the trenches
103
cannot be reduced excessively. That is, since the distance between the trenches
103
cannot be reduced below a given value, the hole flow resistance cannot be increased on the basis only of a decreasing in this distance.
In the IGBT shown in
FIGS. 20A and 20B
, the other factor that determines the conduction loss in the ON state is the resistance of a channel induced by the gate electrode
104
. The channel resistance can be lowered by increasing the area of a region where the channel is induced, i.e., by increasing the density in the channel region. However, when the distance between the trenches
103
is determined, the density of the p-base layer
102
also increases with increasing channel density. That is, the decrease in channel resistance and promotion of conductivity modulation have tradeoff relationships, and therefore, the conduction loss can be decreased only to a limited level.
Devices with a large current capacity are generally used in parallel connection. In the conventional structure, however, since trench gates are formed at a high density, the electrostatic capacitance between a gate electrode and a main electrode (collector electrode or emitter electrode) becomes large. This electrostatic capacitance causes delay or nonuniformity in switching operation or generates parasitic oscillation.
In the IGBT shown in
FIGS. 20A and 20B
, since the gate-collector capacitance acts as a mirror capacitance in turning off, a period (to be referred to as a mirror period hereinafter) when a predetermined potential difference is held between the gate and the emitter is generated. If the mirror period is long, the energy loss in turning off is large because the energy loss is in proportion to the turn-off time. In addition, during the mirror period, the potential is unstable, and a current readily concentrates in a large-size device or in parallel operation of devices, resulting in lower controllable current of the device.
Hence, the characteristics of the semiconductor device can be improved by shortening the mirror period. However, in the conventional IGBT with a trench gate, a non-current path region
132
which is not connected to the emitter electrode
109
contributes to the gate-collector capacitance. As a consequence, the gate-collector capacitance increases, and the mirror period becomes long.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device with a trench gate, which can increase the hole flow resistance without reducing the distance between trenches and decrease the conduction loss.
It is another object of the present invention to provide a semiconductor device with a trench gate, which can reduce the gate-collector capacitance without increasing the conduction loss.
It is still another object of the present invention to provide a semiconductor device with a trench gate, which can reduce the conduction loss beyond the limit of a prior-art device (increase the channel density and promote conductivity modulation) and also facilitate parallel connection.
According to the first aspect of the present invention, there is provided a semiconductor device with a trench gate, comprising:
a first semiconductor layer of first conductivity type;
a second semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to inject carriers of second conductivity type into the first semiconductor layer;
a third semiconductor layer of second conductivity type, which is arranged on the first semiconductor layer, to collect the carriers of second conductivity type in the first semiconductor layer from the first semiconductor layer;
a pair of trench portions extending through the third semiconductor layer and reaching the first semiconductor layer;
a pair of gate electrode portions disposed in the pair of trench portions via gate insulating films, respectively;
a pair of fourth semiconductor layer portions of first conductivity type, which are formed along the pair of trench portions, respectively, in a surface portion of the third semiconductor layer interposed between the pair of trench portions, each of the fourth semiconductor layer portions being arranged to inject carriers of first conductivity type through a channel induced in the third semiconductor layer by the gate electrode portion into the first semiconductor layer and cause conductivity modulation therein;
a first main electrode disposed in contact with the second semiconductor layer;
a second main electrode disposed in contact with the third semiconductor layer and fourth semiconductor layer portions; and
a narrowing tren

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