Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2008-03-25
2008-03-25
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S113000, C257SE21596
Reexamination Certificate
active
11473081
ABSTRACT:
A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.
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Japanese Office Action issued in corresponding Japanese Patent Application No. 2002-200930, dated May 18, 2007.
Japanese Office Action issued in corresponding Japanese Patent Application No. 2002-200930, mailed Feb. 27, 2007.
Michii Kazunari
Semba Shinji
Shinonaga Naoyuki
Booth Richard A.
McDermott Will & Emery LLP
Renesas Technology Corp.
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