Semiconductor device with strain

Details Semiconductor device with strain Semiconductor device with strain

2004-10-22

2008-09-09

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S213000, C257S288000, C257S368000, C257S369000, C257S506000, C257S629000, C257S632000, C257SE27060, C257SE27062, C257SE29020

Reexamination Certificate

active

07423330

ABSTRACT:
A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

REFERENCES:
patent: 6943391 (2005-09-01), Chi et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6982465 (2006-01-01), Kumagai et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2004/0075148 (2004-04-01), Kumagai et al.
patent: 2004/0251479 (2004-12-01), Tsutsui et al.
patent: 2005/0230756 (2005-10-01), Chang et al.
patent: 2003-86708 (2003-03-01), None
patent: 2003-273240 (2003-09-01), None
Shinya Ito et al., IEDM 2000 Tech. Dig., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, pp. 247-250, 2000.
F. Ootsuka et al., IEDM 2000 Tech. Dig., “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications”, pp. 575-578, 2000.
A. Shimizu et al., IEDM 2001 Tech. Dig., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, pp. 433-436, 2001.
Yukihiro Kumagai et al., SSDM 2002, “Evaluation of change in drain current due to strain in 0.13-μm-node MOSFETs”, pp. 14-15, 2002.

Affiliated with

Also associated with

Rating

Semiconductor device with strain does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device with strain, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with strain will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3967631